參數(shù)資料
型號： UPSD3254BV-40T1
廠商： 意法半導體
英文描述： POWERLINE: RP30-S_DE - 2:1 Wide Input Voltage Range- 30 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- International Safety Standard Approvals- Ul 1950 Component Recognised- Standard 50.8 x40.6x10.2mm Package- Efficiency to 90%
中文描述： 閃存可編程系統(tǒng)設備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù)： 157/176頁
文件大?。?/td> 1214K
代理商： UPSD3254BV-40T1
157/176
μPSD325X DEVICES
Figure 78. Input to Output Disable / Enable
Table 121. CPLD Combinatorial Timing (5V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t
PD
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Table 122. CPLD Combinatorial Timing (3V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t
PD
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
1
Unit
t
PD2
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
+ 2
+ 10
– 2
ns
t
EA
CPLD Input to CPLD Output
Enable
21
+ 10
– 2
ns
t
ER
CPLD Input to CPLD Output
Disable
21
+ 10
– 2
ns
t
ARP
CPLD Register Clear or Preset
Delay
21
+ 10
– 2
ns
t
ARPW
CPLD Register Clear or Preset
Pulse Width
10
+ 10
ns
t
ARD
CPLD Array Delay
Any
macrocell
11
+ 2
ns
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
1
Unit
t
PD2
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
40
+ 4
+ 20
– 6
ns
t
EA
CPLD Input to CPLD Output
Enable
43
+ 20
– 6
ns
t
ER
CPLD Input to CPLD Output
Disable
43
+ 20
– 6
ns
t
ARP
CPLD Register Clear or
Preset Delay
40
+ 20
– 6
ns
t
ARPW
CPLD Register Clear or
Preset Pulse Width
25
+ 20
ns
t
ARD
CPLD Array Delay
Any
macrocell
25
+ 4
ns
tER
tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
相關PDF資料
PDF描述
UPSD3253BV-40T1T Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
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參數(shù)描述
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