參數(shù)資料
型號： uPSD3412C-40U6T
廠商： 意法半導(dǎo)體
英文描述： 320 x 240 pixel format, CFL backlight available with power harness
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和16Kbit SRAM的
文件頁數(shù)： 65/152頁
文件大?。?/td> 1558K
代理商： UPSD3412C-40U6T
65/152
UPSD3212C, UPSD3212CV
More About Modes 2 and 3.
Eleven
transmitted (through TxD), or received (through
RxD): a Start Bit (0), 8 data bits (LSB first), a pro-
grammable 9th data bit, and a Stop Bit (1). On
transmit, the 9th data bit (TB8) can be assigned
the value of '0' or '1.' On receive, the data bit goes
into RB8 in SCON. The baud rate is programma-
ble to either 1/16 or 1/32 the CPU clock frequency
in Mode 2. Mode 3 may have a variable baud rate
generated from Timer 1.
Figure 31, page 66 and Figure 33, page 67 show
a functional diagram of the serial port in Modes 2
and 3. The receive portion is exactly the same as
in Mode 1. The transmit portion differs from Mode
1 only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal also loads TB8 into the 9th bit po-
sition of the transmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission commences at S1P1 of the machine
cycle following the next roll-over in the divide-by-
16 counter. (Thus, the bit times are synchronized
to the divide-by-16 counter, not to the “WRITE to
SBUF” signal.)
The transmission begins with activation of SEND,
which puts the start bit at TxD. One bit time later,
DATA is activated, which enables the output bit of
the transmit shift register to TxD. The first shift
pulse occurs one bit time after that (see Figure 32,
page 66 and Figure 34, page 67). The first shift
clocks a '1' (the Stop Bit) into the 9th bit position of
the shift register. There-after, only zeros are
clocked in. Thus, as data bits shift out to the right,
zeros are clocked in from the left. When TB8 is at
the out-put position of the shift register, then the
Stop Bit is just to the left of TB8, and all positions
to the left of that contain zeros. This condition flags
the TX Control unit to do one last shift and then de-
bits
are
activate SEND and set TI. This occurs at the 11th
divide-by 16 rollover after “WRITE to SUBF.”
Reception is initiated by a detected 1-to-0 transi-
tion at RxD. For this purpose RxD is sampled at a
rate of 16 times whatever baud rate has been es-
tablished. When a transition is detected, the di-
vide-by-16 counter is immediately reset, and 1FFH
is written to the input shift register.
At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of R-D.
The value accepted is the value that was seen in
at least 2 of the 3 samples. If the value accepted
during the first bit time is not '0,' the receive circuits
are reset and the unit goes back to looking for an-
other 1-to-0 transition. If the Start Bit proves valid,
it is shifted into the input shift register, and recep-
tion of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to
the left. When the Start Bit arrives at the left-most
position in the shift register (which in Modes 2 and
3 is a 9-bit register), it flags the RX Control block
to do one last shift, load SBUF and RB8, and set
RI.
The signal to load SBUF and RB8, and to set RI,
will be generated if, and only if, the following con-
ditions are met at the time the final shift pulse is
generated:
1. RI = 0, and
2. Either SM2 = 0, or the received 9th data bit = 1
If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes
into RB8, and the first 8 data bits go into SBUF.
One bit time later, whether the above conditions
were met or not, the unit goes back to looking for
a 1-to-0 transition at the RxD input.
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