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參數(shù)資料
| 型號： | UT6164C |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 異步靜態(tài)RAM高速 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 84K |
| 代理商： | UT6164C |
UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC.
P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE (TA=25, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
CIN
-
8
pF
Input/Output Capacitance
CI/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL=30pF, IOH/IOL=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS (V
CC = 5V
10% , TA = 0Jto 70J)
(1) READ CYCLE
UT6164C-10
UT6164C-12
UT6164C-15 UNIT
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
tRC
10
-
12
-
15
-
ns
Address Access Time
tAA
-
10
-
12
-
15
ns
Chip Enable Access Time
tACE
-
10
-
12
-
15
ns
Output Enable Access Time
tOE
-
5
-
6
-
7
ns
Chip Enable to Output in Low Z
tCLZ*
2
-
3
-
4
-
ns
Output Enable to Output in Low Z
tOLZ*
0
-
0
-
0
-
ns
Chip Disable to Output in High Z
tCHZ*
-
5
-
6
-
7
ns
Output Disable to Output in High Z
tOHZ*
-
5
-
6
-
7
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
ns
(2) WRITE CYCLE
UT6164C-10
UT6164C-12
UT6164C-15
UNIT
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
tWC
10
-
12
-
15
-
ns
Address Valid to End of Write
tAW
8
-
10
-
12
-
ns
Chip Enable to End of Write
tCW
8
-
10
-
12
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Write Pulse Width
tWP
8
-
9
-
10
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
ns
Data to Write Time Overlap
tDW
6
-
7
-
8
-
ns
Data Hold from End of Write Time
tDH
0
-
0
-
0
-
ns
Output Active from End of Write
tOW*
2
-
3
-
4
-
ns
Write to Output in High Z
tWHZ*
-
6
-
7
-
8
ns
*These parameters are guaranteed by device characterization, but not production tested.
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