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參數(shù)資料
| 型號(hào)： | UT6164C |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 異步靜態(tài)RAM高速 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | UT6164C |
UTRON
UT6164C
Rev. 1.1
8K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC.
P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
t WC
t AW
t CW1
t AS
t WP
t WH
t OW
t DW
t DH
t CW2
t WR
Address
CE1
CE2
WE
Dout
Din
Data Valid
High-Z
(4)
WRITE CYCLE 2 (
1
CE BCE2 Controlled) (1,2,5)
t WC
t AW
t CW1
t AS
t WR
t CW2
t WP
t WHZ
t DW
t DH
Data Valid
Address
CE1
CE2
WE
Dout
Din
High-Z
Notes :
1.
or
1 must be high or CE2 must be low during all address transitions.
2.
A write occurs during the overlap of a low
1 , a high CE2 and a low
.
3. During a
controlled with write cycle with
low, tWP must be greater than tWHZ+tDW to allow the I/O drivers
to turn off and data to be placed on the bus.
4.
During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
1 low and CE2 high transition occurs simultaneously with or after
low transition, the outputs remain in a high
impedance state.
6.
tOW and tWHZ are specified with CL=5pF. Transition is measured
500mV from steady state.
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