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Fiber Optics
V23814/15-K1306-M230 Parallel Optical Link: PAROLI
Tx/Rx DC
3
START-UP PROCEDURE
Detailed information can be found in the data sheet of the Paroli
test board AC/DC, part number V23814-S1306-M931 and
V23815-S1306-M931.
Switch system power supply on and hold -RESET at Low
level
Release -RESET when V
CC
has reached 3.0 V level and clock
input is stable
Delay 100 ms until laser controller and PLL have settled
After 100 ms MU and LCU will be high
Apply data input
Module starts transmitting.
LE/-LE can be used to activate/deactivate laser output at any
time. For data transmission they must be activated. If the LE
and -LE module pins are not connected, then laser output is
automatically activated.
TECHNICAL DATA
The electro-optical characteristics described in the following
tables are valid only for operation under the recommended
operating conditions.
Recommended Operating Conditions
Notes
Voltages refer to V
EE
=0 V.
1. Noise frequency is 1 kHz to 10 MHz. Voltage is peak-to-peak value.
2. Noise frequency is > 10 MHz. Voltage is peak-to-peak value.
3. Level diagram
Figure 3. Input level diagram
4. |V
ID
|=
|
(input voltage of non-inverted input minus input voltage of
inverted input)
|.
5. 20% - 80% level.
6. Measured between 0.8 V and 2.0 V.
7 Lower limit of clock frequency due to PLL frequency limitations.
8. Measured at 50% level.
9. The unit interval UI refers to a strobe cycle in this case.
1 UI = 1/f
CLOCK
in Strobe Mode and 1 UI = 1/(2
·
f
CLOCK
) in SCI
Mode
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
Noise on Power Supply
(1)
Noise on Power Supply
(2)
V
CC
N
PS1
N
PS2
V
LVDSI
3.0
3.6
V
50
mV
100
LVDS Input
Voltage Range
(3)
500
1900
LVDS Input Differential
Voltage
(3, 4)
|V
ID
|
100
1000
LVDS Clock Input
Rise/Fall Time
(5)
t
R
, t
F
100
400
ps
LVCMOS Input
High Voltage
V
LVCMOSIH
2.0
V
CC
V
LVCMOS Input
Low Voltage
V
LVCMOSIL
V
EE
0.8
LVCMOS Input Rise/
Fall Time
(6)
t
R
, t
F
20
ns
Clock Input Frequency,
SCI Mode
(7)
f
CLOCK
75
250
MHz
Clock Input Frequency,
Strobe Mode
(7)
f
CLOCK
150
500
MHz
Clock Input Duty
Cycle Distortion
dcd
45
55
%
Input Skew between
Clock Inputs
(8)
t
SPN
0.75 x
t
R
, t
F
0.1
ps
Clock Input
Total Jitter
(pk-pk)(9)
CJ
UI
mV
1900
500
Time
|VID|