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參數(shù)資料
| 型號： | V23814-K1306-M230 |
| 英文描述： | FIBER OPTIC TRANSMITTER |
| 中文描述： | 光纖變送器 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | V23814-K1306-M230 |
Fiber Optics
V23814/15-K1306-M230 Parallel Optical Link: PAROLI
Tx/Rx DC
7
DESCRIPTION
Receiver V23815-K1306-M230
The PAROLI receiver module converts parallel optical input
signals (data and frame) into parallel electrical output signals.
Figure 8. Receiver block diagram
All electrical data and clock outputs are LVDS compatible. The
module also features several LVCMOS compatible control
inputs and outputs, which are described in the Receiver Pin
Description (table starting on page 10).
The module features demultiplexing and decoding of 11 optical
data input channels to 22 electrical data output channels. The
frame signal is used to control an integrated PLL circuit, which
generates internal clock signals for decoding and demultiplex-
ing. The PLL circuit also generates a clock signal at the Receiver
output.
Transmission delay of the PAROLI system is at a maximum of
4 strobe cycles + 3 ns for the transmitter, 3 strobe cycles + 3 ns
for the receiver, and approximately 5 ns per meter for the fiber
optic cable.
Clocking Modes
The receiver can be operated in one of two output clocking
modes: Strobe mode or SCI mode. The mode is selected via
CLK_SEL input. In Strobe mode, the rising edges of the non-
inverted clock signal are centered over the data bits. In SCI
mode, High/Low transitions of clock and data signals coincide.
In SCI mode the electrical interface complies with the SCI stan-
dard. See Timing diagram Figure 10.
Decoding and Demultiplexing
The input data received from the optical interface are strobed
into the input register with the PLL generated internal clock sig-
nal. The data are read in relation to FRAME input. The input fre-
quency expected at FRAME is one fifth of square input data
frequency, as FRAME transitions indicate 5B word boundaries.
FRAME input is expected to change levels simultaneously with
data transitions.
All eleven input data channels are fed through individual 5B/4B
decoders. Decoding is based on an inversion bit which is
received at the first position of a 5B word. This bit determines
whether the nibble received at bit positions 2, 3, 4 and 5 has to
be inverted. An inversion bit High level indicates a nibble which
was transmitted uninverted, i.e. this 4B nibble will be directly
forwarded to the demultiplexer. If the inversion bit received is
Low, the corresponding nibble will be inverted by the decoder
before it is demultiplexed.
The 4B words from the decoders are then demultiplexed 1:2 to
electrical output data channels. Output channels 1 to 11 are
grouped with output channels 12 to 22, i.e. optical data input 1
feeds electrical data outputs 1 and 12; optical data input 2 feeds
electrical data outputs 2 and 13, etc.
Demultiplexing of a 4B word (with bits #1...#4) takes two data
output cycles.
During the first cycle, bit #1 is presented at the lower data out-
put (1...11) and bit #2 at the higher data output (12...22). During
the second cycle, bits #3 and #4 are presented at the lower and
higher outputs, respectively.
(Example: Of the 4B word from optical data channel 1, bit #1 is
presented at corresponding lower data output 1 and bit #2 is
presented at corresponding higher data output 12.)
The demultiplexed data bits are presented as 22 parallel out-
puts together with the output clock signal, the characteristics of
which depend on the clocking mode. (See Clocking Modes
above.)
Start-up Procedure
Detailed information can be found in the data sheet of the Paroli
Test board AC/DC, part number V23815-S1306-M931.
Switch system power supply on and hold -RESET at Low
level
Release -RESET when V
CC
has reached 3.0 V level
Wait for LOCK_DET to become High
Module starts presenting data at the data outputs if OE is
High.
If OE is at a high level or left open during start-up, clock output
will start running immediately after release of -RESET. Clock fre-
quency will drift upwards to the operating frequency estab-
lished by FRAME input when FRAME_DET indicates sufficient
input signal level. After PLL has locked (indicated by LOCK_DET
high level) data outputs are also enabled. OE can be used for
complete LVDS switch-off whenever clock drift during start-up
is critical.
CLK_SEL
-RESET
PLL
Output
Stage
Decoder
Demulti-
plexer
Ampli-
fier
Pin
Diode
Array
11
11
22
11
22
ENSD
OE
FRAME_DET
LOCK_DET
-SD11
Data
Outputs
Clock
Output
Frame
Fiber
Data
Fibers
Optical
Inputs
Electrical
Outputs
Frame
Clock
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| V23814-U1306-M130 | 功能描述:PARALLEL OPTICAL LINK 1.6GBIT RoHS:否 類別:光電元件 >> 光纖 - 發(fā)射器 - 驅動器集成電路 系列:- 標準包裝:8 系列:- 波長:- 數(shù)據(jù)速率:1.6Gbps 功率 - 輸出:- 電源電壓:3.3V 應用:電信 電流 - 電源:- 其它名稱:V23814-U1306IN |
| V23814-U1306-M136 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PAROLI Tx AC, 1.6 Gbit/s |
| V23814-Z6-Z1 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Heatsink for PAROLI Backplane Module |
| V23815-K1306-M136 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PAROLI Tx AC, 1.25 Gbit/s |
| V23815-K1306-M230 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FIBER OPTIC RECEIVER |
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