參數(shù)資料
型號(hào)： V23818-H18-L47
元件分類： 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 10/14頁(yè)
文件大小： 1007K
代理商： V23818-H18-L47
Fiber Optics
V23814/15-K1306-M230 Parallel Optical Link: PAROLI
Tx/Rx DC
10
Figure 11. Measurement conventions for LVDS signals
Setup and Hold Times
Setup and hold times are measured between the cross point of
positive and negative clock and the points where rising and fall-
ing data edge cross the borders of the V-range.
Figure 12. Numbering conventions receiver
The numbering conventions for the Tx and Rx modules are the same.
Receiver Pin Description
Pin#
Pin Name
Level/Logic Description
1
V
EE
V
CC1
Ground
2
Power supply voltage of
preamplifier
3
V
CC2
Power supply voltage of analog
circuitry
4
t.b.l.o.
to be left open
5
-RESET
LVCMOS in
low active
High=receiver is active.
Low=internal logic is reset and
LVDS outputs are set to low.
Internal pull- up pulls to
high level when this input is
left open.
6
FRAME_
DET
LVCMOS
Out
High=FRAME input signal
present (on fiber #1)
Low=insufficient FRAME
signal
7
V
CC3
Power supply voltage of
digital circuitry
8
V
EE
V
CC4
Ground
9
Power supply voltage of
decoder
10
LOCK_
DET
LVCMOS
Out
High=PLL has successfully
locked onto incoming FRAME
signal. LOCK_DET being low
sets all LVDS data outputs to
low; clock output is unaffected
by LOCK_DET.
11
COP
LVDS Out
Clock Output, non-inverted
12
CON
LVDS Out
Clock Output, inverted
13
DO01P
LVDS Out
Data Output #1, non-inverted
14
DO01N
LVDS Out
Data Output #1, inverted
t
SETUP
t
HOLD
Data
Clock
P
N
|V
OD
| min.
15
DO12P
LVDS Out
Data Output #12, non-inverted
16
DO12N
LVDS Out
Data Output #12, inverted
17
DO02P
LVDS Out
Data Output #2, non-inverted
18
DO02N
LVDS Out
Data Output #2,inverted
19
DO13P
LVDS Out
Data Output #13, non-inverted
20
DO13N
LVDS Out
Data Output #13, inverted
21
DO03P
LVDS Out
Data Output #3, non-inverted
22
DO03N
LVDS Out
Data Output #3, inverted
23
DO14P
LVDS Out
Data Output #14, non-inverted
24
DO14N
LVDS Out
Data Output #14, inverted
25
V
CC4
Power supply voltage of
decoder
26
DO04P
LVDS Out
Data Output #4, non-inverted
27
DO04N
LVDS Out
Data Output #4, inverted
28
V
EE
DO15P
Ground
29
LVDS Out
Data Output #15, non-inverted
30
DO15N
LVDS Out
Data Output #15, inverted
31
DO05P
LVDS Out
Data Output #5, non-inverted
32
DO05N
LVDS Out
Data Output #5, inverted
33
DO16P
LVDS Out
Data Output #16, non-inverted
34
DO16N
LVDS Out
Data Output #16, inverted
35
DO06P
LVDS Out
Data Output #6, non-inverted
36
DO06N
LVDS Out
Data Output #6, inverted
37
DO17P
LVDS Out
Data Output #17, non-inverted
38
DO17N
LVDS Out
Data Output #17, inverted
39
DO07P
LVDS Out
Data Output #7, non-inverted
40
DO07N
LVDS Out
Data Output #7, inverted
41
DO18P
LVDS Out
Data Output #18, non-inverted
42
DO18N
LVDS Out
Data Output #18, inverted
43
DO08P
LVDS Out
Data Output #8, non-inverted
44
DO08N
LVDS Out
Data Output #8, inverted
45
V
EE
DO19P
Ground
46
LVDS Out
Data Output #19, non-inverted
47
DO19N
LVDS Out
Data Output #19, inverted
48
V
CC4
Power supply voltage of
decoder
49
DO09P
LVDS Out
Data Output #9, non-inverted
50
DO09N
LVDS Out
Data Output #9, inverted
51
DO20P
LVDS Out
Data Output #20, non-inverted
52
DO20N
LVDS Out
Data Output #20, inverted
53
DO10P
LVDS Out
Data Output #10, non-inverted
54
DO10N
LVDS Out
Data Output #10, inverted
55
DO21P
LVDS Out
Data Output #21, non-inverted
56
DO21N
LVDS Out
Data Output #21, inverted
57
DO11P
LVDS Out
Data Output #11, non-inverted
58
DO11N
LVDS Out
Data Output #11, inverted
59
DO22P
LVDS Out
Data Output #22, non-inverted
60
DO22N
LVDS Out
Data Output #22, inverted
Pin#
Pin Name
Level/Logic Description
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