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參數(shù)資料
| 型號： | V23818-H18-L47 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 1007K |
| 代理商： | V23818-H18-L47 |
Fiber Optics
V23814/15-K1306-M230 Parallel Optical Link: PAROLI
Tx/Rx DC
9
Notes
Optical parameters valid for each channel.
1. BER=10
–
12
at infinite ER. This means that the sensitivity specifica-
tion equals -13.7 dBm for an input signal with an ER of 5 dB.
2. P
FDA
: Average optical power when FRAME_DET switches from Low
to High.
P
FDD
: Average optical power when FRAME_DET switches from
High to Low.
Values are also applicable for SD11 function, except SD11 is low
active.
Figure 10. Timing diagrams
Strobe Mode
SCI Mode
In this operation mode the clock output is supplied in phase to data
outputs.
Note
1. All data outputs and clock output.
FRAME_DET and -RESET Timing Diagrams
Notes
1. Timing also applicable for SD11 function on fiber #12.
2. Stable frame input required. -RESET not activated.
3. Except when used as power-on reset. At any failure recovery,
-RESET should be brought to low level for at least t
3
.
4. Valid if -RESET is set high when V
CC
exceeds 3.0 V level and optical
FRAME (FRAME_DET=high) and data input are valid. t
5
starts when
all these conditions are fulfilled. -RESET must be set to Low during
power-up.
Parameter
Symbol
Min.
Max.
Units
Sensitivity
(Average Power)
(
1)
P
IN
–
16.5
dBm
Saturation
(Average Power)
P
SAT
–
6.0
FRAME Detect
Assert Level
(
2)
P
FDA
–
18.0
FRAME Detect
Deassert Level
(
2)
P
FDD
–
28.0
FRAME Detect
Hysteresis
(
2)
P
FDA
–
P
FDD
A
RL
1.0
4.0
dB
Return Loss
of Receiver
12
Parameter
Symbol
Min. Typ. Max.
Units
Output Setup Time
t
1
t
2
625
ps
Output Hold Time
Parameter
Output Skew
(1)
Symbol
Min. Typ. Max.
Units
t
s
810
ps
t1
t2
Data In 1...22
Clock Out
P
N
|V
OD
| min.
tS
tS
Data Out 1...22
Clock Out
P
N
|V
OD
| min.
Parameter
Sym-
bol
Min.
Max.
Units
FRAME_DET
Deassert time
(1)
t
1
10
μs
FRAME_DET
Assert Time
(1)
t
2
FRAME_DET Low to
LOCK_DET Low Delay
t
3
20
ns
FRAME_DET High
to LOCK_DET
High Duration
(2)
-RESET Low Duration
(3)
t
4
50
ms
t
5
t
6
t
7
t
8
t
9
100
μs
-RESET Off Delay Time
-RESET On Delay Time
(4)
20
ns
50
ms
LVDS Output Disable Time
20
ns
LVDS Output Enable Time
20
0.4 V
Optical FRAME
Input
FRAME_DET
2.5 V
LOCK_DET
t1
t2
t3
t4
t6
t7
-RESET
Data and
Clock out
valid
2.0 V
0.8 V
Data Low
Clock Low
valid
t5
t8
t9
OE
Data and
Clock out
valid
2.0 V
0.8 V
Data Low
Clock Low
valid
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