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參數(shù)資料
| 型號： | V3020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ultra Low Power 1-Bit 32 kHz RTC |
| 中文描述： | 超低功耗1位32 kHz的時鐘 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 470K |
| 代理商： | V3020 |
Status Information
The RAM addresses 0 and 1 contain status and control data for
the V3020. The function of each bit (0 and 7) within address
locations 0 and 1 is shown in Tables 7a and 7b respectively.
Reset and Initialization
Upon microprocessor recovery from a system reset, the V3020
must be initialized by software in order to guarantee that it is
expecting a communication cycle (i.e the internal serial buffer is
waiting for the address bit A0). Software can initialize the V 3020
to expect a communication cycle by executing 8
microprocessor reads (see Fig. 10).
Initializing Access to the V3020
10
On first startup or whenever power has failed (V
status register 0 and the clock must be initialized by software.
Having initialized the interface to expect the address bit A0,
write 0 to status register 0, then set the clock (see section “Clock
and Calendar”).
Time and Date Status Bits
There are time and date status bits at address 1 in the RAM.
Upon executing a Copy_clock_to_RAM command, the time and
date status bits in the RAM show which time and date
parameters changed since the last time this command was
used. A logic 1 in the seconds status bit (address 1, bit 0) in the
RAM indicates that the seconds location in the RAM (address 2)
changed since the last Copy_clock_to_RAM command and
thus needs to be read. The seconds location must change
before any other time or date location can change. If the
seconds status bit is clear, then no time or date location
changed since the last Copy_clock_to_RAM command and so
the RAM need not to be read by software.
Table 7b shows the seconds, minutes, hours, day of the month,
month, year, week day, and week number status bit locations.
They are set or cleared similar to the seconds location. It should
be noted that if the minutes status bit is clear, then the seconds
bit may be set, but all other status bits are clear. Similarly with
hours, the bits representing the units less than hours may have
been set, but the bits for the higher units will be clear. This rule
holds true for the week day or day of month locations also.
The time and date status bits can be used to drive software
routines which need to be executed every
- second,
- minute,
- hour,
- day of month / week day,
- month,
- year,
or
- week.
In this application it is necessary to poll the V 3020 at least once
every time interval used as it does not generate an interrupt.
Upon executing a Copy_RAM_to_clock command, the time and
date status bits in the RAM are cleared.
Time Set Lock
The time set lock control bit is located at address 0, bit 4 (see
Table 7a). When set by software, the bit disables the
Copy_RAM_to_clock command (see section “Commands”.) A
set bit prevents unauthorized overwriting of the current time and
date in the clock. Clearing the time set lock bit by software will
re-enable the Copy_RAM_to_clock command. On first startup
or whenever power has failed (V
must be setup by software.
< 1.2 V) the
DD
< 1.2 V), the time set lock bit
DD
Status Word
Table 7a
Status 0 - address 0
Read / Write bits
Frequency Measurement Mode
Reserved
Test Mode 0
Test Mode 1
Time Set Lock
Reserved
Reserved
Reserved
0 - inactive
1 - active
7 6 5 4 3 2 1 0
Table 7b
Status 1 - address 1
Read ONLY bits
Seconds
Minutes
Hours
Day of month
Month
Year
Week day
Week number
0 - No change from last
Copy_clock_to_RAM
1 - Change from last
Copy_clock_to_RAM
7 6 5 4 3 2 1 0
CS
RD
WR
I/O
m
P reads 8 times
D0
D1
D7
Fig. 10
V3020
R
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