參數(shù)資料
型號(hào): V436616Y04VTGL-75
英文描述: x64 SDRAM Module
中文描述: X64的內(nèi)存模塊
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 64K
代理商: V436616Y04VTGL-75
4
V436616Y04VTG-75 Rev. 1.0 August 2000
MOSEL VITELIC
V436616Y04VTG-75
Serial Presence Detect Information
A serial presence detect storage device -
E
PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
SPD-Table for 75 modules:
2
written into the E
duction using a serial presence detect protocol (I
synchronous 2-wire bus)
2
PROM device during module pro-
2
C
Byte Number
Function Described
SPD Entry Value
Hex Value
16Mx64
0
Number of SPD bytes
128
80
1
Total bytes in Serial PD
256
08
2
Memory Type
SDRAM
04
3
Number of Row Addresses (without BS bits)
13
0D
4
Number of Column Addresses (for x16 SDRAM)
9
09
5
Number of DIMM Banks
1
01
6
Module Data Width
64
40
7
Module Data Width (continued)
0
00
8
Module Interface Levels
LVTTL
01
9
SDRAM Cycle Time at CL=3
7.5 ns
75
10
SDRAM Access Time from Clock at CL=3
5.4 ns
54
11
Dimm Config (Error Det/Corr.)
none
00
12
Refresh Rate/Type
Self-Refresh, 15.6
μ
s
80
13
SDRAM width, Primary
x16
10
14
Error Checking SDRAM Data Width
n/a / x8
00
15
Minimum Clock Delay from Back to Back Random
Column Address
t
ccd
= 1 CLK
01
16
Burst Length Supported
1, 2, 4, 8, full page
8F
17
Number of SDRAM Banks
4
04
18
Supported CAS Latencies
CL = 3
04
19
CS Latencies
CS Latency = 0
01
20
WE Latencies
WL = 0
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
22
SDRAM Device Attributes: General
Vcc tol ± 10%
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
Not Supported
00
24
Maximum Data Access Time from Clock for CL = 2
Not Supported
00
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
26
Maximum Data Access Time from Clock at CL = 1
Not Supported
00
27
Minimum Row Precharge Time
20 ns
14
28
Minimum Row Active to Row Active Delay t
RRD
15 ns
0F
29
Minimum RAS to CAS Delay t
RCD
20 ns
14
30
Minimum RAS Pulse Width t
RAS
45 ns
2D
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