參數(shù)資料
型號: V436616Y04VTGL-75
英文描述: x64 SDRAM Module
中文描述: X64的內(nèi)存模塊
文件頁數(shù): 5/12頁
文件大?。?/td> 64K
代理商: V436616Y04VTGL-75
MOSEL VITELIC
V436616Y04VTG-75
5
V436616Y04VTG-75 Rev. 1.0 August 2000
DC Characteristics
T
A
= 0
°
C to 70
°
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
±
0.3V
31
Module Bank Density (Per Bank)
128 Mbyte
20
32
SDRAM Input Setup Time
1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup Time
1.5 ns
15
35
SDRAM Data Input Hold Time
0.8 ns
08
62-61
Superset Information (May be used in Future)
00
62
SPD Revision
Revision 2
02
63
Checksum for Bytes 0 - 62
A5
64
Manufacturer’s JEDEC ID Code
Mosel Vitelic
40
65-71
Manufacturer’s JEDEC ID Code (cont.)
00
72
Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436616Y04VTG-75
91-92
PCB Identification Code
Current PCB Revision
93
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 = MSB
99-127
Reserved
00
128+
Unused Storage Location
00
Symbol
Parameter
Limit Values
Unit
Min.
Max.
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
V
IL
Input Low Voltage
–0.5
0.8
V
V
OH
Output High Voltage (I
OUT
= –4.0 mA)
2.4
V
V
OL
Output Low Voltage (I
OUT
= 4.0 mA)
0.4
V
I
I(L)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
–40
40
μ
A
I
O(L)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
–40
40
μ
A
SPD-Table for 75 modules: (Continued)
Byte Number
Function Described
SPD Entry Value
Hex Value
16Mx64
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