參數(shù)資料
型號： V436616Y04VTGL-75
英文描述： x64 SDRAM Module
中文描述： X64的內(nèi)存模塊
文件頁數(shù)： 7/12頁
文件大?。?/td> 64K
代理商： V436616Y04VTGL-75
MOSEL VITELIC
V436616Y04VTG-75
7
V436616Y04VTG-75 Rev. 1.0 August 2000
AC Characteristics
T
A
= 0° to 70
°
C; V
SS
= 0V; V
CC
= 3.3V
±
0.3V, t
T
= 1 ns
#
Symbol
Parameter
Limit Values
Unit
Note
-75
Min.
Max.
Clock and Clock Enable
1
t
CK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
10
–
–
s
ns
ns
2
t
CK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
100
MHz
MHz
3
t
AC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
_
5.4
6
ns
ns
2, 4
4
t
CH
Clock High Pulse Width
2.5
–
ns
5
t
CL
Clock Low Pulse Width
2.5
–
ns
6
t
T
Transition Tim
0.3
1.2
ns
Setup and Hold Times
7
t
IS
Input Setup Time
1.5
–
ns
5
8
t
IH
Input Hold Time
0.8
–
ns
5
9
t
CKS
Input Setup Time
1.5
–
ns
5
10
t
CKH
CKE Hold Time
0.8
–
ns
5
11
t
RSC
Mode Register Set-up Time
15
–
ns
12
t
SB
Power Down Mode Entry Time
0
7.5
ns
Common Parameters
13
t
RCD
Row to Column Delay Time
20
–
ns
6
14
t
RP
Row Precharge Time
20
–
ns
6
15
t
RAS
Row Active Time
45
100K
ns
6
16
t
RC
Row Cycle Time
60
–
ns
6
17
t
RRD
Activate(a) to Activate(b) Command Period
15
–
ns
6
18
t
CCD
CAS(a) to CAS(b) Command Period
1
–
CLK
Refresh Cycle
19
t
REF
Refresh Period (8192 cycles)
—
64
ms
20
t
SREX
Self Refresh Exit Time
10
ns
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