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參數(shù)資料
| 型號： | V53C16129H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 128K X 16 BIT FAST PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 128K的高性能× 16位快速頁面模式的CMOS動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 223K |
| 代理商： | V53C16129H |
MOSEL VITELIC
1
V53C16129H
HIGH PERFORMANCE
128K x 16 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C16129H Rev. 1.2 July 1997
HIGH PERFORMANCE
40
45
50
60
Max. RAS Access Time, (t
RAC
)
40 ns
45 ns
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
20 ns
22 ns
24 ns
30 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
15 ns
17 ns
19 ns
27 ns
Min. Read/Write Cycle Time, (t
RC
)
75 ns
80 ns
90 ns
110 ns
Features
I
128K x 16-bit organization
I
EDO Page Mode for a sustained data rate
of 67 MHz
I
RAS access time: 40, 45, 50, 60 ns
I
Dual CAS Inputs
I
Low Power Dissipation
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
I
Refresh Interval: 512 cycles/8ms
I
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
I
Single +5V
±
10% Power Supply
I
TTL Interface
Description
The V53C16129H is a 131,072 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C16129H offers Page mode with
Extended Data Output. EDO Page Mode operation
allows random access up to 512 x 16 bits, within a
page, with cycle times as short as 15 ns. An
address, CAS and RAS input capacitances are
reduced to minimize the loading. The V53C16129H
has asymmetric address 8-bit row and 9-bit
column.
All inputs are TTL compatible. The V53C16129H
is best suited for graphics, and DSP applications
requiring high performance memories.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
40
45
50
60
Std.
0
°
C to 70
°
C
Blank
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|---|---|
| V53C16129LK60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
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| V53C16256HK50 | 制造商:Mosel Vitelic Corporation 功能描述: 制造商:VIT/MOSE 功能描述: |
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