參數(shù)資料
型號: V53C16256
廠商: Mosel Vitelic, Corp.
英文描述: 256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM
中文描述: 256K × 16快速頁面模式的CMOS動態(tài)隨機存儲器
文件頁數(shù): 17/19頁
文件大?。?/td> 146K
代理商: V53C16256
17
MOSEL V ITELIC
V53C16256H
V53C16256H Rev. 2.3 June 1998
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(t
DS
) to be satisfied.
Power-On
After application of the V
CC
supply, an initial
pause of 200
m
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement of
the V53C16256H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and I
CC
will exhibit
current transients. It is recommended that RAS and
CAS track with V
CC
or be held at a valid V
IH
during
Power-On to avoid current surges.
Table 1. V53C16256H Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write)
High-Z
Fast Page Mode Read-
Modify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
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