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參數(shù)資料
| 型號： | V53C318160A |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 Volt 1M X 16 Fast Page Mode CMOS Dynamic RAM(3.3V 1Mx16快速頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 3.3伏100萬× 16快速頁面模式的CMOS動態(tài)RAM（3.3 1Mx16快速頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 174K |
| 代理商： | V53C318160A |
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MOSEL V ITELIC
1
V53C318160A
3.3 VOLT 1M X 16 FAST PAGE MODE
CMOS DYNAMIC RAM
V53C318160A Rev. 1.4 March 1998
HIGH PERFORMANCE
50
60
70
Max. RAS Access Time, (t
RAC
)
50 ns
60 ns
70 ns
Max. Column Address Access Time, (t
CAA
)
25 ns
30 ns
35 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
35 ns
40 ns
45 ns
Min. Read/Write Cycle Time, (t
RC
)
90 ns
104 ns
124 ns
Features
I
1M x 16-bit organization
I
Fast Page Mode for a sustained data rate
of 29 MHz
I
RAS access time: 50, 60, 70 ns
I
Dual CAS Inputs
I
Low power dissipation
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh, and
Self Refresh.
I
Refresh Interval: 1024 cycles/16 ms
1024 cycles/256 ms (L-version)
I
Available in 42-pin 400 mil SOJ and 50/44-pin
400 mil TSOP-II
I
Single +3.3 V
±
0.3 V Power Supply
I
LVTTL Interface
Description
The V53C318160A is a 1048576 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C318160A offers Fast Page mode op-
eration. The V53C318160A has an symmetric
address, 10-bit row and 10-bit column.
All inputs are LVTTL compatible. Fast Page
Mode operation allows random access up to 1024 x
16 bits, within a page, with cycle times as short as
35 ns.
These features make the V53C318160A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
50
60
70
Std.
L
0
°
C to 70
°
C
Blank
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