參數(shù)資料
型號(hào)： V53C318160A
廠商： Mosel Vitelic, Corp.
英文描述： 3.3 Volt 1M X 16 Fast Page Mode CMOS Dynamic RAM(3.3V 1Mx16快速頁面模式CMOS動(dòng)態(tài)RAM)
中文描述： 3.3伏100萬× 16快速頁面模式的CMOS動(dòng)態(tài)RAM（3.3 1Mx16快速頁面模式的CMOS動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 23/28頁
文件大?。?/td> 174K
代理商： V53C318160A
MOSEL V ITELIC
V53C318160A
23
V53C318160A Rev. 1.4 March 1998
Functional Description
The V53C318160A is a CMOS dynamic RAM op-
timized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C318160A reads and writes
data by multiplexing an 20-bit address into a 10-bit
row and a 10-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
ed or aborted before the minimum t
RAS
time has ex-
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t
RP
/t
CP
has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
mum specified by t
AR
. Data Out becomes valid only
when t
OAC
, t
RAC
, t
CAA
and t
CAC
are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by t
CAA
when t
RAC
,
t
CAC
and t
OAC
are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and t
OED
must be satisfied.
Fast Page Mode
Fast Page operation permits all 1024 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the occur-
rence of a valid column address rather than from the
falling edge of CAS, eliminating t
ASC
and t
T
from the
critical timing path. CAS latches the address into the
column address buffer. During Fast Page operation,
Read, Write, Read-Modify-Write or Read-Write-
Read cycles are possible at random addresses
within a row. Following the initial entry cycle into
EDO Mode, access is t
CAA
or t
CAP
controlled. If the
column address is valid prior to the rising edge of
CAS, the access time is referenced to the CAS ris-
ing edge and is specified by t
CAP
. If the column ad-
dress is valid after the rising CAS edge, access is
timed from the occurrence of a valid address and is
specified by t
CAA
. In both cases, the falling edge of
CAS latches the address and enables the output.
Fast Page provides a sustained data rate of 29
MHz for applications that require high bandwidth
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
Self Refresh
Self Refresh mode provides internal refresh con-
trol signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimi-
nation of external refresh control signals. Self Re-
fresh mode is initialed with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (t
RASS
)
and CAS low (t
CHD
) for a specified period. Both of
these parameters are specified with minimum val-
ues to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to main-
tain Self Refresh operation.
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (t
RPS
)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiat-
ed immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
Data Rate
1024
1023
t
RC
t
PC
×
+
-------------------------------------------
=
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