- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359324 > V53C516165A (Mosel Vitelic, Corp.) 5 Volt 1M X 16 EDO Page Mode CMOS Dynamic RAM(5V 1Mx16 EDO頁面模式CMOS動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | V53C516165A |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 5 Volt 1M X 16 EDO Page Mode CMOS Dynamic RAM(5V 1Mx16 EDO頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 5伏100萬× 16 EDO公司頁面模式的CMOS動態(tài)RAM（5V的1Mx16 EDO公司頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 174K |
| 代理商： | V53C516165A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁
24
V53C516165A Rev. 1.0 March 1998
MOSEL V ITELIC
V53C516165A
Data Output Operation
The V53C516165A Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(t
DS
) to be satisfied.
Power-On
After application of the V
CC
supply, an initial
pause of 200
μ
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement of
the V53C516165A is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and I
CC
will ex-
hibit current transients. It is recommended that RAS
and CAS track with V
CC
or be held at a valid V
IH
dur-
ing Power-On to avoid current surges.
Table 1. V53C516165A Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write Cycle
(Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle (Early Write)
High-Z
EDO Read-Modify-Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
High-Z
CAS-only Cycles
High-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V53C516400A50 | R/A(M) JUMPER 1.32MM 300" BLK |
| V53C516400A60 | TOOLS, HAND CRIMP RoHS Compliant: Yes |
| V53C516400A | 4M x 4 Fast Page Mode CMOS Dynamic RAM(4Mx4快速頁面模式CMOS動態(tài)RAM) |
| V53C516405A50 | 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM |
| V53C516405A60 | 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V53C664K80L | 制造商:Mosel Vitelic Corporation 功能描述:64K X 16 FAST PAGE DRAM, 80 ns, PDSO40 |
| V53C8256HP45 | 制造商:Mosel Vitelic Corporation 功能描述: |
| V53C864K10L | 制造商:VITELIC 功能描述: |
| V53C864K80L | 制造商:VITELIC 功能描述: |
| V5-4/RK 4-0.3/0.3/0.3 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 4m, PVC, Yellow |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。