參數(shù)資料
型號(hào)： V54C365804VCT8L
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 8M X 8 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù)： 45/54頁
文件大?。?/td> 453K
代理商： V54C365804VCT8L
5
V54C365804VC Rev. 0.6 September 1999
MOSEL VITELIC
V54C365804VC
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Notes:
1.
V = Valid , x = Don’t Care, L = Low Level, H = High Level
2.
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3.
These are state of bank designated by BS0, BS1 signals.
4.
Device state is Full Page Burst operation
5.
Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock
suspend mode.
Operation
Device
State
CKE
n-1
CKE
nCS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Row Activate
Idle3
HX
L
H
X
V
Read
Active3
H
X
LHLHX
V
L
V
Read w/Autoprecharge
Active3
H
X
LHLHX
V
H
V
Write
Active3
H
X
LHL
L
X
V
L
V
Write with Autoprecharge
Active3
H
X
LHL
L
X
V
H
V
Row Precharge
Any
H
X
L
H
L
X
L
V
Precharge All
Any
H
X
L
H
L
X
H
X
Mode Register Set
Idle
H
X
LLLLX
V
No Operation
Any
H
X
L
H
X
Device Deselect
Any
H
X
H
X
Auto Refresh
Idle
H
L
H
X
Self Refresh Entry
Idle
H
L
H
X
Self Refresh Exit
Idle
(Self Refr.)
L
H
XXX
XX
X
LH
H
X
Power Down Entry
Idle
Active5
HL
H
XXX
XX
X
LH
H
X
Power Down Exit
Any
(Power
Down)
LH
H
XXX
XX
X
LH
HL
Data Write/Output Enable
Active
H
X
XXXX
L
X
Data Write/Output Disable
Active
H
X
XXXX
H
X
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