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參數(shù)資料
| 型號(hào)： | V58C2128 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| 中文描述： | 高性能2.5伏128兆位DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 7/59頁 |
| 文件大?。?/td> | 948K |
| 代理商： | V58C2128 |
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7
MOSEL VITELIC
V58C2128(804/404/164)S
V58C2128(804/404/164)S Rev. 1.6 March 2002
Address Bus
CAS Latency
A
6
A
5
0
0
0
0
1
1
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
Reserve
0
0
1
1
0
0
1
1
Reserve
2.5
Reserve
Burst Length
A
2
A
1
A
0
Latency
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A
7
0
1
mode
Normal
Test
A
3
0
1
Burst Type
Sequential
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
A
8
0
1
DLL Reset
No
Yes
Mode Register Set
0
RFU : Must be set "0"
Extended Mode Register
Mode Register
DLL
I/O
QFC
A
0
0
1
DLL Enable
Enable
Disable
A
2
0
1
QFC Control
Disable
Enable
A
1
0
1
I/O Strength
Full
Half
BA
0
0
1
A
n
~ A
0
(Existing)MRS Cycle
Extended Funtions(EMRS)
Command
2
0
1
5
3
4
8
6
7
CK, CK
t
CK
t
MRD
Precharge
All Banks
Mode
Register Set
t
RP
*2
*1
Any
Command
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
TM
CAS Latency
BT
Burst Length
RFU
DLL
MRS
MRS
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA
0
(The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A
0
~ A
11
in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet t
MRD
spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
, addressing mode
uses A
3
, CAS latency (read latency from column address) uses A
4
~ A
6
. A
7
is a Mosel Vitelic specific test
mode during production test. A
8
is used for DLL reset. A
7
must be set to low for normal MRS operation. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1.
MRS can be issued only at all banks precharge state.
2.
Minimum tRP is required to issue MRS command.
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PDF描述 |
|---|---|
| V58C2128164S | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2128404S | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2128804S | HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C265164S | 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C2128164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2128404S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2128804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2256 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
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