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| 型號： | V62C5181024LL-70P |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70% |
| 中文描述： | 200萬× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 24/43頁 |
| 文件大?。?/td> | 1155K |
| 代理商： | V62C5181024LL-70P |
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K4S643232C
CMOS SDRAM
REV. 1.1 Nov. '99
- 24
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
CS
RAS
CAS
WE
ADDR
ACTION
Note
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
OP Code
X
X
X
X
X
Self
Refresh
INVALID
Exit Self Refresh --> Idle after t
RFC
(ABI)
Exit Self Refresh --> Idle after t
RFC
(ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
6
6
7
7
8
8
8
9
9
All
Banks
Idle
*Note :
6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + t
SS
must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.
Abbreviations : ABI = All Banks Idle, RA = Row Address
CKE
(n-1)
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
CKE
n
All
Banks
Precharge
Power
Down
Any State
other than
Listed
above
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