參數(shù)資料
型號： V91F565U24QCFW-F5
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝： ROHS COMPLIANT, FBDIMM-240
文件頁數(shù)： 8/22頁
文件大?。?/td> 207K
代理商： V91F565U24QCFW-F5
V91F565U24QC Rev 1.0 May 2007
16
V91F565U24QC
ProMOS TECHNOLOGIES
Absolute Maximum DC Ratings
Symbol
Min
Typical
Max
Units
Notes
DRAM VDD / VDDQ, AMB VDDQ
1.7
1.8
1.9
V
AMB VCC / VCCFBD
1.46
1.5
1.54
V
1
DRAM Interface VTT
0.48 x VDD
0.5 x VDD
0.52 x VDD
V
VDDSPD
3.0
3.3
3.6
V
Note 1: Estimate
DC Electrical Characteristics and Operating Conditions
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)
Symbol
Parameter
Min
Max
Units
Notes
VDD
Supply Voltage
1.7
1.9
V
1
VDDQ
I/O Supply Voltage
1.7
1.9
V
1
VSS, VSSQ
Supply Voltage, I/O Supply Voltage
0
V
VREF
I/O Reference Voltage
0.49 x
VDDQ
0.51 x
VDDQ
V
1, 2
VTT
I/O Termination Voltage (System)
VREF - 0.04
VREF + 0.04
V
1, 3
VIH (DC)
Input High (Logic1) Voltage
VREF + 0.125
VDDQ + 0.3
V
1
VIL (DC)
Input Low (Logic0) Voltage
-0.3
VREF - 0.125
V
1
VIN (DC)
Input Voltage Level, CK and
Inputs
-0.3
VDDQ + 0.3
V
1
VID (DC)
Input Differential Voltage, CK and
Inputs
0.30
V DDQ + 0.6
V
1, 4
IIL
Input Leakage Current
Any input 0V < VIN < VDD; (All other pins not under test = 0V)
-5
5
uA
1
IOZ
Output Leakage Current
(DQs are disabled; 0V < Vout < VDDQ
-5
5
uA
1
Note:
1.
Inputs are not recognized as valid until VREF stabilizes.
2.
VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
3.
VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,
and must track variations in the DC level of VREF.
4.
VID is the magnitude of the difference between the input level on CK and the input level on .
AC Operating Conditions
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
VIH (AC) Input High (Logic 1) Voltage
V REF + 0.31
-
V
1, 2
VIL (AC)
Input Low (Logic 0) Voltage
-
V REF - 0.31
V
1, 2
VID (AC) Input Differential Voltage, CK and
Inputs
0.7
V DDQ + 0.6
V
1, 2, 3
VIX (AC)
Input Differential Pair Cross Point Voltage, CK and
Inputs
0.5 x VDDQ - 0.2
0.5 x VDDQ + 0.2
V
1, 2, 4
1.
Input slew rate = 1V/ ns.
2.
Inputs are not recognized as valid until VREF stabilizes.
3.
VID is the magnitude of the difference between the input level on CK and the input level on
.
4.
The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same.
--
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