參數(shù)資料
型號: VECANA01
英文描述: 10-Channel, 12-Bit DATA ACQUISITION SYSTEM
中文描述: 10通道,12位數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 15/17頁
文件大?。?/td> 329K
代理商: VECANA01
15
VECANA01
SBAS155
CONNECTION BETWEEN VECANA01 AND DSP
The interface between the VECANA01 and dSMC101 com-
prises the control signals for the A/D converters (ADCLK,
ADCONV, ADIN, ADOUT1-3, NPSH, ADBUSY and
DATACLK) and the comparator signals (X_COMP and
X_ILIM). The signal levels and the driver capacity of the
two chips are compatible. In order to avoid noise injection of
the digital power supply into the analog VECANA01 chip,
it is recommended to damp all digital lines with an interme-
diate resistor of approximately 100
as near as possible to
the analog chip.
Motor
Control
DSP
VECANA01
100
FIGURE 8. Damping of All Digital Lines.
Sican
dSMC101
VECANA01
U/V/W_COMP
U/V/W_ILIM
A_1, B_1
A_2, B_2
ADCLK
ADCONV
ADOUT1-3
ADIN
NPSH
Phase-
Currents
IUP/N
IVP/N
IWP/N
A1P/N
B1P/N
A2P/N
B2P/N
AN1P/N
AN2P/N
AN3P/N
Encoder1
Encoder2
Auxillary
Inputs
FIGURE 9. DSP Interface for Sican dSMC101.
FIGURE 7. Power Supply of VECANA01.
+
C
R
C
R
C
B
C
A
+
C
B
C
A
+
C
B
C
D
+
C
B
C
D
+
C
A
5.6V
OUT
IN
OUT
IN
+U
B
–U
B
+
C
A
REFIN
VECANA01
REFOUT
UP5V
UDP5V
AGND
DGND
REFGND
UDN5V
UN5V
R
A
R
D
R
D
R
A
Ground Plane
Voltage Regulator,
Current Limited
5.6V
–5V
+5V
SICAN dSMC101 INTERFACE
The internal logic of the VECANA01 is designed for easy
control and data interface with DSPs. Figure 9 shows the
interface for loading the input control word from the DSP
data bus into the serial input of the VECANA01.
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