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參數(shù)資料
| 型號： | VECANA01 |
| 英文描述： | 10-Channel, 12-Bit DATA ACQUISITION SYSTEM |
| 中文描述： | 10通道，12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 329K |
| 代理商： | VECANA01 |
9
VECANA01
SBAS155
FIGURE 2. Timing Diagram.
ADCLK (Input)
ADCONV (Input)
SAMPLE (Internal)
ADBUSY (Output)
DAC Input 0-7
1
14
1
2
t
CONV
t
SAMPLE
7
6
5
4
3
2
1
0
1
0
2
1
0
Gain
Select
0-1
Input
Select
0-2
ADOUT1
ADIN
How Used
NOTE: (1) See the specification table for timing specifications. (2) 50% duty cycle.
Clock Pulse
Reference No.
CLOCK AND
CONTROL SIGNALS
(1)
DATACLK (Output)
A-to-D
CONVERTER OUTPUTS
CONTROL WORD INPUT
ADOUT2
ADOUT3
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 0
Bit 0
Bit 0
Bit 0
Bit 11
LSB
LSB
LSB
2
3
4
5
6
7
8
9
10
11
12
13
t
1
t
2
t
5
t
3
t
4
MULTIPLEXERS
The VECANA01 has several input multiplexers that are
used to select the desired analog inputs and connect the
proper sample-and-hold outputs to the PGAs and A/D con-
verters. A decoder receives its inputs from the Input Setup
Register and drives the MUXs (see Table VII and Table VIII
for information on selecting the input channel). The input
multiplexers can take full differential or single-ended signals
(see Figure 4 and Table III). The analog signals stay differ-
ential through the sample holds and the PGAs all the way to
the inputs of the A/D converter. This provides the best
possible noise rejection.
SAMPLE-AND-HOLD
The VECANA01 contains seven sample-and-hold amplifiers.
Five of them (SH
1
through SH
5
) sample simultaneously and
have their sample-and-hold timing internally synchronized
(the timing is shown in Figure 2). Three of the sample-and-
holds (SH
1
, SH
3
, and SH
5
) are connected to the input multi-
plexers so that they can provide simultaneous sampling for all
of their channel inputs. In addition, SH
2
and SH
4
simulta-
neously sample the third input of their channel (A2 and
B2, respectively). This is useful in motor control applications
where A1 and B1 are the quadrature inputs for one position
sensor, and A2 and B2 are the quadrature inputs for a second
position sensor (see Figure 9). In that application, it is desir-
able to sample the quadrature inputs of a given position sensor
at the same time (even though they are converted on succes-
sive conversion cycles) (see Table VII), so that their values are
captured at the same shaft position. The VECANA01 also has
the capability for limited asynchronous sampling. The sam-
pling of SH
6
and SH
7
is controlled asynchronously by the
control signal NPSH (see Table VII). This allows two inputs,
each on Channel 1 and Channel 2 (see Table VIII) to be
sampled asynchronously from the timing of the other sample
holds. This can be useful in motor control applications where
the two inputs for each channel need to be sampled asynchro-
nously to a reference point.
ADCS AND PGAS
The VECANA01 contains three signal channels each with a
12-bit A/D converter output. The A/D converters operate
synchronously and their serial outputs occur simultaneously
(Table IX gives the analog input/digital output relationships).
Programmable gain amplifiers precede the A/D converters
(Table IX gives gain select information). For channels one and
two, the PGAs are effective for all three analog inputs. For the
third channel, only the IW input is gain changed by the PGA.
Inputs AN1, AN2, and AN3 are connected to the A/D con-
verter three at a fixed gain of 1.0V/V regardless of the gain
select value.
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