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參數(shù)資料
| 型號： | VG26V17400CJ-5 |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 4 FAST PAGE DRAM, 50 ns, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-26/24 |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 310K |
| 代理商： | VG26V17400CJ-5 |
Document:1G5-0087
Rev.4
Page 13
VIS
VG26(V)(S)17400C
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Notes :
1. AC measurements assume tT = 5ns.
2. An initial pause of 100
is required after power up, and it followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is
used, a minimum of eight CAS-before-RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltage.
5. tRAS(min) = tRWD(min) + tRWL(min) + tT in read - modify-write cycle.
6. tCAS(min) = tCWD(min) + tCWL(min) + tT in read - modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min) and tRPC are determined by the falling edge of CAS.
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS.
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
12. Assumes that tRCD
tRCD(max) and tRAD
tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
13. Assumes that tRCD
tRCD(max) and tRAD
tRAD(max).
14. Access time is determined by the maximum among tAA, tCAC, tCPA.
15. Assumes that tRCD
tRCD(max) and tRAD
tRAD(max).
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (
high impedance).
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS
tWCS(min), the cycle is an early write cycle and the
data output will remain open circuit (high impedance) throughout the entire cycle. If tRWD
tRWD(min),
tCWD
tCWD(min), tAWD
tAWD(min), and tCPW
tCPW(min), the cycle is a read-modify-write and the
data output will contain data read from the selected cell. If neither of the above sets of conditions is
satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS in an early write cycle and to WE edge in a delayed write or a
read-modify-write cycle.
20. tRASP defines RAS pulse width in Fast page mode cycles.
s
≤
≥
≤
≥
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相關(guān)代理商/技術(shù)參數(shù) |
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| VG26V17400DJ-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| VG26V17400DJ-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM|FAST PAGE|4MX4|CMOS|SOJ|26PIN|PLASTIC |
| VG26V17400DT-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| VG26V17400DT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| VG26V17400EJ-5 | 制造商:VML 制造商全稱:VML 功能描述:4,194,304 x 4 - Bit CMOS Dynamic RAM |
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