參數(shù)資料
型號: VG36641641DT-6
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Synchronous Dynamic RAM
中文描述: 同步動態(tài)隨機存儲器的CMOS
文件頁數(shù): 26/69頁
文件大?。?/td> 1364K
代理商: VG36641641DT-6
Document :1G5-0177
Rev.2
Page 26
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Burst lengh= X
CLK
Command
CAS latency=2
DQ
Hi-Z
Read
T0
T1
T2
T3
T4
T5
T6
T7
T8
PRE
ACT
DQ
Read
PRE
ACT
t
RP
CAS latency=3
Q0
Q3
Q2
Q1
Hi-Z
Q0
Q3
Q2
Q1
command
t
RP
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