參數(shù)資料
型號: VP5311C
廠商: Zarlink Semiconductor Inc.
英文描述: NTSC/PAL Digital Video Encoder
中文描述: NTSC / PAL數(shù)字視頻編碼器
文件頁數(shù): 3/19頁
文件大?。?/td> 317K
代理商: VP5311C
VP5311C/VP5511C
2
66.83
1.050
27k
1.3699
24.93
50
33.75
17.64
1.40
7.62
7.62
0.40
34.15
18.71
26.73
8.02
8.02
0.00
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS
VIH
VIL
VIH
VIL
IIH
IIL
VOH
VOL
VOL
2.0
0.7 VDD
3.7
0.8
0.3 VDD
10
-10
0.4
0.6
V
V
V
V
μ
A
μ
A
V
V
V
Parameter
Conditions
VIN = VDD
VIN = VSS
IOH = -1mA
IOL = +4mA
IOL = +6mA
Symbol
Min.
Typ.
Max.
Units
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS DACs
INL
DNL
V
REF
Z
R
I
REF
K
DAC
±
1.5
±
1
±
5
LSB
LSB
%
μ
A
V
mA
pV-s
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter
Symbol
Min.
Typ.
Max.
Units
Accuracy (each DAC)
Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity
LSB size
Internal reference voltage
Internal reference voltage output impedance
Reference Current (V
REF
/R
REF
) R
REF
= 769
DAC Gain Factor (V
OUT
= K
DAC
x I
REF
x R
L
), V
OUT
= DAC code 511
Peak Glitch Energy (see fig.3)
CVBS, Y and C - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
CVBS, Y and C - PAL
Maximum output
White level relative to black level
White level relative to sync level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)
Note:
All figures are for: R
REF
= 769
R
L
= 37.5
. When the device is set up in NTSC mode there is a +0.25% error in the PAL
levels. If R
L
= 75
then R
REF
= 1538
.
ABSOLUTE MAXIMUM RATINGS
Supply voltage
VDD, AVDD
-0·3 to 7·0V
Voltage on any non power pin
-0·3 to VDD+0·3V
Ambient operating temperature
0 to 70
°
C
Storage temperature
-55
°
C to 150
°
C
Digital Inputs TTL compatible (except SDA, SCL)
Input high voltage
Input low voltage
Digital Inputs SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Digital Outputs CMOS compatible
Output high voltage
Output low voltage
Digital Output SDA
Output low voltage
guaranteed
Note: Stresses exceeding these listed under Absolute
Maximum Ratings may induce failure. Exposure to Absolute
Maximum Ratings for extended periods may reduce
reliability. Functionality at or above these conditions is not
implied.
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