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參數(shù)資料
| 型號(hào)： | VP5311C |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | NTSC/PAL Digital Video Encoder |
| 中文描述： | NTSC / PAL數(shù)字視頻編碼器 |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | VP5311C |
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VP5311C/VP5511C
5
Pin Name
Pin No.
Description
PD7-0
30 - 37
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
37. These pins are internally pulled low.
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 1.
These pins are internally pulled low.
27MHz Pixel Clock input. The VP5311C/5511C internally divides PXCK by two to provide the
pixel clock.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC and PAL-M; lines 6-310 and 319-623
for PAL-B,D, G,I,N(Argentina)).
Composite sync pulse output. This is an active low output signal.
D0-7
1 - 8
PXCK
12
CLAMP
14
COMPSYNC
15
TDO
TDI
TMS
TCK
SA1
SA2
SCL
SDA
RESET
16
17
18
19
21
22
23
25
27
JTAG Data output port.
JTAG Data input port.
JTAG mode select input.
JTAG clock input.
I
2
C slave address select
I
2
C slave address select.
Standard I
2
C bus serial clock input.
Standard I
2
C bus serial data input/output.
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5311C/5511C.
Reference square wave input used only during Genlock mode.
Voltage reference input/output. This pin is nominally 1.055V and should be decoupled with a
100nF capacitor to GND.
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.
DAC compensation. A 100nF ceramic capacitor must be connected between pin 43 and pin
44.
True luminance, composite and chrominance video signal outputs. These are high
impedance current source outputs. A DC path to GND must exist from each of these pins.
REFSQ
VREF
28
41
DAC GAIN
42
COMP
43
LUMAOUT
COMPOUT
CHROMAOUT
VDD
45
47
49
10, 13, 24,
26, 39
44, 50,
51, 52
9, 11, 20,
29, 38
40, 46, 48
Positive supply input. All VDD pins must be connected.
AVDD
Analog positive supply input. All AVDD pins must be connected.
GND
Negative supply input. All GND pins must be connected.
AGND
Negative supply input. All AGND pins must be connected.
PIN DESCRIPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VP531 | NTSC/PAL Digital Video Encoder |
| VP5513CG1N | NTSC/PAL Digital Video Encoder |
| VP5513GP1N | NTSC/PAL Digital Video Encoder |
| VP5513 | NTSC/PAL Digital Video Encoder |
| VP5513A1N | NTSC/PAL Digital Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP5311C/CG/GP1N | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:NTSC/PAL Digital Video Encoder |
| VP5311CCGGP1N | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Color Encoder Circuit |
| VP5311CG | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:NTSC/PAL Digital Video Encoder |
| VP5311D/CG/GP1N | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Color Encoder Circuit |
| VP5313 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:NTSC/PAL Digital Video Encoder |
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