參數(shù)資料
型號: VS6524Q06J
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁數(shù): 21/70頁
文件大小: 505K
代理商: VS6524Q06J
VL6524/VS6524
Output frame size control
21/70
integration time available slower frame rates have improved performance in low light
conditions.
6.2.1
Horizontal mirror and vertical flip
The image data output from the VL6524/VS6524 can be mirrored horizontally or flipped
vertically (or both).
These functions are available in the
Pipe setup bank0 control
register bank.
6.3
ViewLive Operation
ViewLive is an option which allows different size, format and image settings to be applied to
alternate frames of the output data.
The controls for ViewLive function are found in the View live controlregister bank where the
fEnableregister allows the host to enable or disable the function and the
InitalPipeSetupBankregister selects which pipe setup bank is output first (see
Table 18:
View live control
for register description).
Video pipe setup
The key controls for VL6524/VS6524 video pipe setup are grouped into register banks
called
Pipe setup bank0 control
and
Pipe setup bank1 control
.
Pipe setup bank0 control
setup is used when ViewLive is disabled.
When ViewLive is enabled the output data switches between
Pipe setup bank0 control
and
Pipe setup bank1 control
on each alternate frame.
Figure 9.
ViewLive frame output format
Interframe Blanking
Interline
Blanking
Interline
Blanking
Interframe Blanking
Frame output
Active video
Pipe setup bank0
Active Video
Pipe setup bank1
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