參數(shù)資料
型號: VS6524Q06J
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機模塊
文件頁數(shù): 28/70頁
文件大?。?/td> 505K
代理商: VS6524Q06J
Data synchronization methods
VL6524/VS6524
28/70
8.1.3
Mode 2
Table 4.
The structure of a mode 2 image frame is shown
Figure 14
.
Figure 14.
Mode 2 frame structure (VGA example)
For mode 2, the synchronization codes are as listed in
Table 5
.
Table 5.
ITU656 embedded synchronization code definition (odd frames)
Name
Description
4-byte sequence
SAV
Line start - active
FF 00 00 C7
EAV
Line end - active
FF 00 00 DA
SAV (blanking)
Line start - blanking
FF 00 00 EC
EAV (blanking)
Line end - blanking
FF 00 00 F1
Mode 2 - embedded synchronization code definition
Name
Description
4-byte sequence
LS
Line start
FF 00 00 00
LE
Line end
FF 00 00 01
LE
LS
Frame of image data
Line 1
Line 480
Frame blanking period
L
FE
FS
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