參數(shù)資料
型號: VS6524Q06J
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁數(shù): 35/70頁
文件大?。?/td> 505K
代理商: VS6524Q06J
VL6524/VS6524
Host communication - I2C control interface
35/70
Start (S) and Stop (P) conditions
A START (S) condition defines the start of a V2W message. It consists of a high to low
transition on SDA while SCL is high.
A STOP (P) condition defines the end of a V2W message. It consists of a low to high
transition on SDA while SCL is high.
After STOP condition the bus is considered free for use by other devices. If a repeated
START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated
START (Sr) are considered to be functionally equivalent.
Figure 22.
START and STOP conditions
Acknowledge
After every byte transferred the receiver must output an acknowledge bit. To acknowledge
the data byte receiver pulls SDA during the 9th SCL clock cycle generated by the master. If
SDA is not pulled low then the transmitter stops the output of data and releases control of
the bus back to the master so that it can either generate a STOP or a repeated START
condition.
Figure 23.
Data acknowledge
START
condition
STOP
condition
S
P
SDA
SCL
S
1
2
8
9
START condition
Negative acknowledge (A)
Acknowledge (A)
Clock pulse for acknowledge
SDA data output
by transmitter
SDA data output
by receiver
SCL clock from
master
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