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參數(shù)資料
| 型號： | VSC6511 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s |
| 中文描述： | 的SMPTE - 292M的串行器，解串器，并串器/時鐘恢復器/在1.485Gb ? |
| 文件頁數(shù)： | 11/22頁 |
| 文件大小： | 379K |
| 代理商： | VSC6511 |
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 11
4/10/00
VITESSE
Advance Product Information
VSC6511
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
G52311-0, Rev. 2.0
D
Functional Description: Deserializer Mode
The following functional blocks are used in the Deserializer mode of operation. Please refer to the Func-
tional Description at the beginning of this document for the a description of each of these blocks.
Clock Multiplier Unit (CMU)
Serial Input
Clock Recovery Unit
Deserializer
Descrambler and NRZI Decoder
CRC Checker
Frame Aligner and SAV/EAV output
Figure 6: Receive Timing Waveforms (Deserializer Mode)
Table 5: Receive AC Characteristics (Deserializer Mode)
Note: The RCLK output from the CRU is 40% high and 60% low by design.
Parameters
Description
Min.
Max.
Units
Conditions
T
1
TTL Outputs alid prior to
RCLK rise
TTL Outputs valid after
RCLK rise
TTL Output rise and fall
time
Data acquisition lock time
@ 1.485 Gb/s
3.0
—
ns.
T
2
2.0
—
ns.
T
R
, T
F
—
2.0
ns.
Between V
IL(MAX)
and
V
IH(MIN)
, into 10 pf. load.
T
LOCK
—
TBC
ms.
RCLK
D[0:19]
LINE
FRAME
CRCERR
T
2
Data Valid
T
1
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