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參數(shù)資料
| 型號(hào)： | VSC6511 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | SMPTE-292M Serializer, Deserializer, and Deserializer/Reclocker at 1.485Gb/s |
| 中文描述： | 的SMPTE - 292M的串行器，解串器，并串器/時(shí)鐘恢復(fù)器/在1.485Gb ? |
| 文件頁(yè)數(shù)： | 2/22頁(yè) |
| 文件大?。?/td> | 379K |
| 代理商： | VSC6511 |
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VITESSE
Advance Product Information
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
VSC6511
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
4/10/00
G52311-0, Rev 2.0
D
Functional Description
The VSC6511 is a multifunction SMPTE-292M device which can be configured for different modes of
operation: Serializer, Deserializer, or Deserializer/Reclocker. Only one mode is available at a time. A discussion
of the individual building blocks of the device will be followed with specific configurations.
Clock Multiplier Unit (CMU)
The CMU generates the internal 1.485 GHz baud rate clock from the 74.25 MHz TTL REFCLK input. The
rising edges of the REFCLK are used by a PLL which multiplies the frequency by a factor of 20. This internal
baud rate clock is used by the Serializer, Deserializer and Reclocker. An off-chip 0.1uF capacitor sets the loop
bandwidth of the CMU. REFCLK should be a high quality, low jitter signal with sharp rise times in order to
minimize the amount of jitter transferred from the REFCLK through the CMU to the serializer. This optimizes
the signal quality at the output of the serializer.
A secondary function of the CMU is to divide the baud rate clock by 20 to produce an internal 74.25 MHz
clock which is frequency locked and phase aligned to REFCLK. This internal clock is used to latch the 20-bit
data bus D[19:0] into the input register of the Serializer.
REFCLK is also buffered onto the RCLK output when in Serializer or Reclocker mode. This allows multi-
ple devices to be daisy-chained in order to simplify REFCLK distribution to an array of devices.
CRC Generator
The twenty bits of transmit data from the input register is fed into a CRC Generator which calculates the
CRC and substitutes the value into the proper location within the video line. The CRC polynomial is CRC(X)=
(X
18
+ X
5
+ X
4
+ 1). A controller monitors SAV/EAV position and uses this to control the CRC generator and
insertion of the CRC result into the line. The CRC Generator is enabled only in Serializer Mode when CRC is
HIGH. In other modes, or if CRC is LOW, the CRC Generator is disabled and powered down. CRC is a bidi-
rectional pin.
Scrambler and NRZI Encoder
The twenty bits out of the CRC Generator are sent to the parallel Scrambler where the data is scrambled and
NRZI encoded using the combined generator polynomial of G(x)=(x
9
+ x
4
+1)(x+1). Scrambling is enabled
only when in Serializer Mode if SCREN is HIGH. Scrambling is disabled when SCREN is LOW and in other
modes.
Serializer
The data from the Scrambler is converted from 20-bits at 74.25 Mb/s to 1 bit at 1.485 Gb/s by the Serializer
with D0 being transmitted first. Two differential PECL-style serial outputs are provided for transporting the
1.485 Gb/s signal. These outputs SDO0/SDO0 and SDO1/SDO1 are supplied data from the serializer (in Serial-
izer mode) or the CRU of the Reclocker (in Deserializer/Reclocker mode). Each output, SDO0 and SDO1,
have independent TTL inputs, OE0 and OE1, which when HIGH enable the outputs and when LOW disable the
outputs. When disabled, the output buffer will be powered down and both legs will float HIGH.
Each output is compliant with the SMPTE-292M cable driver specification when driving 75 ohm loads. In
this application, a TBD ohm resistor should be connected from the ISET0/ISET1 pin to ground in order to con-
trol the current in the differential output amplifier. By lowering the ISET resistor, higher output swings may be
realized.
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