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參數(shù)資料
| 型號： | W238 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 175K |
| 代理商： | W238 |
W238
Document #: 38-07219 Rev. *A*
Page 3 of 17
Overview
The W238 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel
architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/SEL1 is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. CPU clock outputs will be determined by
the status of FSEL0:1 input pins. An external 10-k
strapping
resistor should be used.
Figure 1
shows a suggested method
for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1
outlines the device functions selectable through
Tristate# and FSEL0:1. Specific outputs available at each pin
are detailed in
Table 2
below.
Notes:
2.
3.
4.
5.
6.
7.
Provided for board-level
“
bed of nails
”
testing.
“
Normal
”
mode of operation.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
Required for DC output impedance verification.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W238
V
DD
Clock Load
10 k
Output
(Load Option 1)
10k
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. CK Solano Truth Table
Tristate#
FSEL1
0
0
1
1
1
1
FSEL0
0
1
0
1
1
1
CPU
Hi-Z
TCLK/4
66 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Hi-Z
TCLK/4
100 MHz
100 MHz
133MHz
100 MHz
3V66
Hi-Z
TCLK/6
66 MHz
66 MHz
66 MHz
66 MHz
PCI
Hi-Z
48MHz
Hi-Z
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
Hi-Z
TCLK
APIC
Hi-Z
TCLK/12
33 MHz
33 MHz
33 MHz
33 MHz
Notes
2
4, 5
3, 6, 7
3, 6, 7
2, 5, 6
2, 5, 6
X
X
0
0
1
1
TCLK/12
33 MHz
33 MHz
33 MHz
33 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W23C4096-12 | x8 ROM (Mask Programmable) |
| W23C4096-15 | x8 ROM (Mask Programmable) |
| W23C4096-20 | x8 ROM (Mask Programmable) |
| W23C8192-12 | x8 ROM (Mask Programmable) |
| W23C8192-15 | x8 ROM (Mask Programmable) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W238-02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| W238E32A | 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Replaced by W238-E1-7 |
| W23C4096-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
| W23C4096-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
| W23C4096-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
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