
W238
Document #: 38-07219 Rev. *A*
Page 9 of 17
W238 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be writ-
ten to a
“
0
”
level.
3. All register bits labeled
“
Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current. The controller will read
back the written value.
Notes:
Notes:
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
15. Spread Spectrum percentage is
–
0.5%.
Byte 0: Control Register (1 = Enable, 0 = Disable)
[14]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin#
-
-
-
-
-
Name
Default
0
0
0
0
0
Pin Function
Reserved
Reserved
Reserved
Reserved
Spread Spectrum
(1 = On/0 = Off)
[15]
DOT
USB
Reserved
Reserved
Reserved
Reserved
Reserved
(Disabled/Enabled)
Bit 2
Bit 1
Bit 0
29
28
-
1
1
0
(Active/Inactive)
(Active/Inactive)
Reserved
Byte 1: Control Register (1 = Enable, 0 = Disable)
[14]
Bit
Pin#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Default
1
1
1
1
1
1
1
1
Pin Description
40
41
44
45
46
47
50
51
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0 = Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
12
31
34
35
38
39
15
--
Name
Default
1
1
1
1
1
1
1
1
Pin Description
3V66_AGP
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
PCI1
Reserved
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)