參數(shù)資料
型號: W25Q32BWZPIP
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 4M X 8 SPI BUS SERIAL EEPROM, DSO8
封裝: 6 X 5 MM, GREEN, WSON-8
文件頁數(shù): 16/72頁
文件大?。?/td> 2212K
代理商: W25Q32BWZPIP
W25Q32BW
Publication Release Date: July 08, 2010
- 23 -
Preliminary - Revision E
10.2.8 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction (Status
Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low,
sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 7.
The Status Register bits are shown in figure 3 and described earlier in this datasheet.
Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1)
and CMP, LB3, LB2, LB1, LB0, QE, SRP1(bits 14 thru 8 of Status Register-2) can be written to. All other
Status Register bit locations are read-only and will not be affected by the Write Status Register
instruction. LB3-0 are non-volatile OTP bits, once it is set to 1, it can not be cleared to 0.
The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not
done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock
(compatible with the 25X series) the CMP, QE and SRP1 bits will be cleared to 0. After /CS is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write
Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again.
After the Write Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register
bits are 0.
Figure 7. Write Status Register Instruction Sequence Diagram
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