參數(shù)資料
型號(hào): W25X40BLSNIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 4M X 1 FLASH 2.7V PROM, PDSO8
封裝: 0.150 INCH, GREEN, PLASTIC, SOIC-8
文件頁(yè)數(shù): 24/53頁(yè)
文件大小: 2041K
代理商: W25X40BLSNIG
W25X10BL/20BL/40BL
- 30 -
9.2.17
Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2). The
Block Erase instruction sequence is shown in figure 17.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,
and BP0) bits (see Status Register Memory Protection table).
Figure 17. Block Erase Instruction Sequence Diagram
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