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參數(shù)資料
| 型號： | W3E232M16S-400STC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W3E232M16S-400STC |
W3E232M16S-XSTX
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most signicant
column address for a given conguration); and by A3-Ai
when the burst length is set to eight. The remaining (least
signicant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the rst bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satised.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to dene the specic mode of
operation of the DDR SDRAM. This denition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specied time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecied operation.
Mode register bits A0-A2 specify the burst length, A3
species the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E232M16S-400STCG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-400STI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-400STIG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-XSTX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E32M64S-200BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
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