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參數(shù)資料
| 型號： | W3E232M16S-400STC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大小： | 0K |
| 代理商： | W3E232M16S-400STC |
W3E232M16S-XSTX
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLL should always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specied time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecied operation.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specied to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.device loses power. The enabling
of the DLL should always be followed by a LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL.The extended mode register
must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specied
time before initiating any subsequent operation. Violating
either of these requirements could result in unspecied
operation.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
CAS
LATENCY = 2
CAS
LATENCY = 2.5
CAS
LATENCY = 3
-200
≤ 75
≤ 100
-
-266
≤ 100
≤ 133
-
-333
≤ 166
-400
-
≤ 166
≤ 200
TABLE 2 - CAS LATENCY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E232M16S-400STCG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-400STI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-400STIG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-XSTX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E32M64S-200BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
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