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參數(shù)資料
| 型號： | W3E32M64S-333BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM, 0.7 ns, PBGA219 |
| 封裝： | 25 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 847K |
| 代理商： | W3E32M64S-333BC |
W3E32M64S-XBX
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 4
RAS0#
WE0#
CAS0#
WE# RAS# CAS#
CLK0#
CLK#
CS0#
CS#
RAS1#
WE1#
CAS1#
WE# RAS# CAS#
CLK1#
CLK#
CS1#
CS#
A0-12
BA0-1
DQ0
DQ15
CKE0
CKE
DQML0
DQML
DQMH0
DQMH
DQ0
DQ15
U1
A0-12
BA0-1
DQ16
DQ31
DQ0
DQ15
U0
CKE1
CKE
DQML1
DQML
DQMH1
DQMH
DQ0
DQ15
U2
A0-12
BA0-1
DQ32
DQ47
CKE2
CKE
RAS2#
WE2#
CAS2#
WE# RAS# CAS#
CLK2#
CLK#
CS2#
CS#
DQML2
DQML
DQMH2
DQMH
RAS3#
WE3#
CAS3#
DQ0
DQ15
WE#
U3
RAS#
A0-12
BA0-1
CLK3#
CLK#
CAS#
DQ48
DQ63
CKE3
CKE
CS3#
CS#
DQSL3
DQSL
DQSH3
DQSH
Y=
CLK3
CLK
VREF
DQSL2
DQSL
DQSH2
DQSH
VREF
DQSL1
DQSL
DQSH1
DQSH
VREF
DQSL0
DQSL
DQSH0
DQSH
CLK2
CLK
CLK1
CLK
CLK0
CLK
VREF
DQML3
DQML
DQMH3
DQMH
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
detect an LVCMOS LOW level after VCC is applied. After CKE
passes through VIH, it will transition to an SSTL_2 signal
and remain as such until power is cycled. Maintaining an
LVCMOS LOW level on CKE during power-up is required
to ensure that the DQ and DQS outputs will be in the
High-Z state, where they will remain until driven in normal
operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the
DDR SDRAM requires a 200μs delay prior to applying an
executable command.
Once the 200μs delay has been satised, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satised.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E32M64S-333BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-333BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-333SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-333SBI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-333SBM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 333 MHZ, 208 PBGA, MIL-TEMP. - Bulk |
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