參數(shù)資料
型號: W3H128M72E0400SBI
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: DDR DRAM, PBGA208
封裝: 16 X 22 MM, 1 MM PITCH, PBGA-208
文件頁數(shù): 19/31頁
文件大?。?/td> 993K
代理商: W3H128M72E0400SBI
W3H128M72E-XSBX
26
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2008
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
(continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Min
Max
Min
Max
Min
Max
Data
DQ hold skew factor
tQHS
-
400
-
400
-
450
ps
DQ output access time from CK/
CK#
tAC
-500
+500
-500
+500
-600
+600
ps
Data-out high impedance window
from CK/CK#
tHZ
tAC(MAX)
ps
DQS Low-Z window from CK/CK#
tLZ1
tAC(MN)
tAC(MAX)
tAC(MN)
tAC(MAX)
tAC(MN)
tAC(MAX)
ps
DQ Low-Z window from CK/CK#
tLZ2
2*tAC(MN)
tAC(MAX)
2*tAC(MN)
tAC(MAX)
2*tAC(MN)
tAC(MAX)
ps
DQ and DM input setup time
relative to DQS
tDSa
350
400
ps
tDHa
350
400
ps
tDSb
100
150
ps
tDHb
225
275
ps
DQ and DM input pulse width (for
each input)
tDIPW
0.35
ps
Data hold skew factor
tQHS
400
450
ps
DQ-DQS hold, DQS to rst DQ to
go nonvalid, per access
tQH
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
ns
Data
Strobe
DQS input high pulse width
tDQSH
0.35*tCK
tCK
DQS input low pulse width
tDQSL
0.35*tCK
tCK
DQS output access time fromCK/
CK#
tDQSCK
-450
+450
-450
+450
-500
+500
ps
DQS falling edge to CK rising -
setup time
tDSS
0.2*tCK
tCK
DQS falling edge from CK rising -
hold time
tDSH
0.2*tCK
tCK
DQS-DQ skew, DOS to last DQ
valid, per group, per access
tDQSQ
240
300
350
ps
DQS read preamble
tRPRE
0.9*tCK
1.1*tCK
0.9*tCK
1.1*tCK
0.9*tCK
1.1*tCK
tCK
DQS read postamble
tRPST
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
tCK
DQS write preamble setup time
tWPRES
000
ps
DQS write preamble
tWPRE
0.35*tCK
0.25*tCK
0.25
tCK
DQS write postamble
tWPST
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
tCK
Positive DQS latching edge to
associated clock edge
tDQSS
-0.25*tCK
0.25*tCK
-0.25*tCK
0.25*tCK
-0.25*tCK
0.25*tCK
tCK
Write command to rst DQS
latching transition
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
tCK
相關PDF資料
PDF描述
W332M64V-100BM 32M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA219
W3EG2256M72ASSR202BJD3ISG 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184
W3EG2256M72ASSR202BJD3SG 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184
W3EG72126S262JD3SG 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
W3H128M72E2-667NBM 128M X 72 DDR DRAM, 0.5 ns, PBGA208
相關代理商/技術參數(shù)
參數(shù)描述
W3H128M72E-400SBC 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk
W3H128M72E-400SBI 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY
W3H128M72E-400SBM 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY
W3H128M72E-533NBI 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA IND TEMP. - Bulk
W3H128M72E-533SBC 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk