- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245651 > W3H128M72E0400SBI (WHITE ELECTRONIC DESIGNS CORP) DDR DRAM, PBGA208 PDF資料下載
參數(shù)資料
| 型號： | W3H128M72E0400SBI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, PBGA-208 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大小： | 993K |
| 代理商： | W3H128M72E0400SBI |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
W3H128M72E-XSBX
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2008
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
CAS LATENCY (CL)
The CAS latency (CL) is dened by bits M4–M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of the
rst bit of output data. The CL can be set to 4, 5 or 6 clocks,
depending on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AL). This feature allows the READ
command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
An example of CL = 4 is shown in Figure 6; assume AL =
0. If a READ command is registered at clock edge n, and
the CL is m clocks, the data will be available nominally
coincident with clock edge n+m (this assumes AL = 0).
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal
t AC, tDQSCK, and tDQSQ
DON’T CARE
TRANSITIONING DATA
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
FIGURE 6 – CAS LATENCY (CL)
相關PDF資料 |
PDF描述 |
|---|---|
| W332M64V-100BM | 32M X 64 SYNCHRONOUS DRAM, 7 ns, PBGA219 |
| W3EG2256M72ASSR202BJD3ISG | 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 |
| W3EG2256M72ASSR202BJD3SG | 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 |
| W3EG72126S262JD3SG | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3H128M72E2-667NBM | 128M X 72 DDR DRAM, 0.5 ns, PBGA208 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3H128M72E-400SBC | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H128M72E-400SBI | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H128M72E-400SBM | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H128M72E-533NBI | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA IND TEMP. - Bulk |
| W3H128M72E-533SBC | 制造商:Microsemi Corporation 功能描述:128M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。