參數(shù)資料
型號(hào): W65C816S8Q-14
元件分類: 16位微控制器
英文描述: 16-Bit Microprocessor
中文描述: 16位微處理器
文件頁(yè)數(shù): 45/62頁(yè)
文件大?。?/td> 891K
代理商: W65C816S8Q-14
WESTERN DESIGN CENTER
W65C816S
March 1, 2000
45
Notes: Be aware that notes #4-7, 9 and 10 apply to the W65C02S and W65C816S. All other notes
apply to the W65C816S only.
1.
Add 1 byte (for immediate only) for M=0 or X=0 (i.e. 16-bit data), add 1 cycle for M=0 or X=0.
REP, SEP are always 3 cycle instructions and VPA is low during the third cycle. The address
bus is PC+1 during the third cycle.
2.
Add 1 cycle for direct register low (DL) not equal 0.
3.
Special case for aborting instruction. This is the last cycle which may be aborted or the Status,
PBR or DBRregisters will be updated.
4.
Add 1 cycle for indexing across page boundaries, or write, or X=0. When X=1 or in the
emulation mode, this cycle contains invalid addresses.
5.
Add 1 cycle if branch is taken.
6.
Add 1 cycle if branch is taken across page boundaries in 6502 emulation mode (E=1).
7.
Subtract 1 cycle for 6502 emulation mode (E=1).
8.
Add 1 cycle for REP, SEP.
9.
Wait at cycle 2 for 2 cycles after NMIB or IRQB active input.
10.
RWB remains high during Reset.
11.
BRK bit 4 equals "0" in Emulation mode.
12.
PHP and PLP.
13.
Some OpCodes shown are compatible only with the W65C816S.
14.
VDA and VPA are not valid outputs on the W65C02S but are valid on the W65C816S. The
two signals, VDA and VPA, are included to point out the upward compatibility to the
W65C816S. When VDA and VPA are both a one level, this is equivalent to SYNC being a one
level.
15.
The PBR is only applicable to the W65C816S.
16.
COP Latches.
17.
In the emulation mode, during a R-M-W instruction the RWB is low during both write and
modify cycles.
AAB Absolute Address Bank
AAH Absolute Address High
AAL Absolute Address Low
AAVH Absolute Address Vector High
AAVL Absolute Address Vector Low
C
Accumulator
D Direct Register
DBA Destination Bank Address
DBR Data Bank Register
DEST Destination
DO Direct Offset
IDH Immediate Data High
IDL Immediate Data Low
IO Internal Operation
OFF
P
PBR
PC
PCH
PCL
R-M-W Read-Modify-Write
REG
Register
S
Stack Address
SBA
Source Bank Address
SRC
Source
SO
Stack Offset
VA
Vector Address
x,y
Index Register
Offset
Status Register
Program Bank Register
Program Counter
Program Counter High
Program Counter Low
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