參數(shù)資料
型號： W65C816S8Q-14
元件分類： 16位微控制器
英文描述： 16-Bit Microprocessor
中文描述： 16位微處理器
文件頁數(shù)： 8/62頁
文件大?。?/td> 891K
代理商： W65C816S8Q-14
WESTERN DESIGN CENTER
W65C816S
March 1, 2000
8
1.6
Data Bank Register (DBR)
During modes of operation, the 8-bit Data Bank Register holds the default bank address for memory transfers. The 24-bit
address is composed of the 16-bit instruction effective address and the 8-bit Data Bank address. The register value is
multiplexed with the data value and is present on the Data/Address lines during the first half of a data transfer memory
cycle for the W65C816S. The Data Bank Register is initialized to zero during Reset.
1.7
Direct (D)
The 16-bit Direct Register provides an address offset for all instructions using direct addressing. The effective bank zero
address is formed by adding the 8-bit instruction operand address to the Direct Register. The Direct Register is initialized
to zero during Reset.
1.8
Index (X and Y)
There are two Index Registers (X and Y) which may be used as general purpose registers or to provide an index value for
calculation of the effective address. When executing an instruction with indexed addressing, the microprocessor fetches
the OpCode and the base address, and then modifies the address by adding the Index Register contents to the address prior
to performing the desired operation. Pre-indexing or post-indexing of indirect addresses may be selected. In the Native
mode (E=0), both Index Registers are 16 bits wide (providing the Index Select Bit (X) equals zero). If the Index Select
Bit (X) equals one, both registers will be 8 bits wide, and the high byte is forced to zero.
1.9
Processor Status (P)
The 8-bit Processor Status Register contains status flags and mode select bits. The Carry (C), Negative (N), Overflow
(V), and Zero (Z) status flags serve to report the status of most ALU operations. These status flags are tested by use of
Conditional Branch instructions. The Decimal (D), IRQ Disable (I), Memory/Accumulator (M), and Index (X) bits are
used as mode select flags. These flags are set by the program to change microprocessor operations.
The Emulation (E) select and the Break (B) flags are accessible only through the Processor Status Register. The
Emulation mode select flag is selected by the Exchange Carry and Emulation Bits (XCE) instruction. Table 8-1,
W65C816S Compatibility Information, illustrates the features of the Native (E=0) and Emulation (E=1) modes. The M
and X flags are always equal to one in the Emulation mode. When an interrupt occurs during the Emulation mode, the
Break flag is written to stack memory as bit 4 of the Processor Status Register.
1.10
Program Bank Register (PBR)
The 8-bit Program Bank Register holds the bank address for all instruction fetches. The 24-bit address consists of the
16-bit instruction effective address and the 8-bit Program Bank address. The register value is multiplexed with the data
bus and presented on the Data bus lines during the first half of a program memory cycle. The Program Bank Register is
initialized to zero during Reset. The PHK instruction pushes the PBR register onto the Stack.
相關(guān)PDF資料
PDF描述
W65C816SP10 Microprocessor
W65C816SP-14 16-Bit Microprocessor
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W65C816SPL-14 16-Bit Microprocessor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W65C816SP10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
W65C816SP-14 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
W65C816SPL10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
W65C816SPL-14 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
W65C816SQ10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
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