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參數(shù)資料
| 型號： | W65C816SQ10 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 15/62頁 |
| 文件大小： | 891K |
| 代理商： | W65C816SQ10 |
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WESTERN DESIGN CENTER
W65C816S
March 1, 2000
15
Table 2-1 Pin Function Table
Pin
Description
A0-A15
Address Bus
ABORTB
Abort Input
BE
Bus Enable
PHI2
Phase 2 In Clock
D0-D7/BA7
Data Bus/Bank Address Bus
E
Emulation Select
IRQB
Interrupt Request
MLB
Memory Lock
MX
Mode Select
NC
No Connect
NMIB
Non-Maskable Interrupt
RDY
Ready
RESB
Reset
RWB
Read/Write
VDA
Valid Data Address
VPB
Vector Pull
VPA
Valid Program Address
VDD
Positive Power Supply (+5 volts)
VSS
Internal Logic Ground
2.1
Abort (ABORTB)
The Abort input is used to abort instructions (usually due to an Address Bus condition). A negative transition
will inhibit modification of any internal register during the current instruction. Upon completion of this
instruction, an interrupt sequence is initiated. The location of the aborted OpCode is stored as the return address
in stack memory. The Abort vector address is 00FFF8,9 (Emulation mode) or 00FFE8,9 (Native mode). Note
that ABORTB is a pulse-sensitive signal; i.e., an abort will occur whenever there is a negative pulse (or level) on
the ABORTB pin during a PHI2 clock.
2.2
Address Bus (A0-A15)
These sixteen output lines form the Address Bus for memory and I/O exchange on the Data Bus. When using the
W65C816S, the address lines may be set to the high impedance state by the Bus Enable (BE) signal.
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