參數(shù)資料
型號： W65C816SQ10
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 25/62頁
文件大小： 891K
代理商： W65C816SQ10
WESTERN DESIGN CENTER
W65C816S
March 1, 2000
25
Table 3-2 Addressing Mode Summary
Address Mode
Instruction Times in Memory
Cycle
Memory Utilization in
Number of Program Sequence
Bytes
Original 8-bit
NMOS 6502
New W65C816S
Original 8-bit
NMOS 6502
New
W65C816
S
1. Immediate
2
2 (3)
2
2 (3)
2. Absolute
4 (5)
4 (3,5)
3
3
3. Absolute Long
-
5 (3)
-
4
4. Direct
3 (5)
3 (3,4,5)
2
2
5. Accumulator
2
2
1
1
6. Implied
2
2
1
1
7. Direct Indirect Indexed (d),y
5 (1)
5 (1,3,4)
2
2
8. Direct Indirect Indexed Long [d],y
-
6 (3,4)
-
2
9. Direct Indexed Indirect (d,x)
6
6 (3,4)
2
2
10. Direct, X
4 (5)
4 (3,4,5)
2
2
11. Direct, Y
4
4 (3,4)
2
2
12. Absolute, X
4 (1,5)
4 (1,3,5)
3
3
13. Absolute Long, X
-
5 (3)
-
4
14. Absolute, Y
4 (1)
4 (1,3)
3
3
15. Relative
2 (1,2)
2 (2)
2
2
16. Relative Long
-
3 (2)
-
3
17. Absolute Indirect (Jump)
5
5
3
3
18. Direct Indirect
-
5 (3,4)
-
2
19. Direct Indirect Long
-
6 (3,4)
-
2
20. Absolute Indexed Indirect (Jump)
-
6
-
3
21. Stack
3-7
3-8
1-3
1-4
22. Stack Relative
-
4 (3)
-
2
23. Stack Relative Indirect Indexed
-
7 (3)
-
2
24. Block Move X,Y,C (Source,
Destination, Block Length)
-
7
-
3
Notes (these are indicated in parentheses):
1.
Page boundary, add 1 cycle if page boundary is crossed when forming address.
2.
Branch taken, add 1 cycle if branch is taken.
3.
M = 0 or X = 0, 16 bit operation, add 1 cycle, add 1 byte for immediate.
4.
Direct register low (DL) not equal zero, add 1 cycle.
5.
Read-Modify-Write, add 2 cycles for M = 1, add 3 cycles for M = 0.
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