參數(shù)資料
型號(hào)： W6692ACF
廠商： WINBOND ELECTRONICS CORP
元件分類： 數(shù)字傳輸電路
英文描述： DATACOM, ISDN CONTROLLER, PQFP100
封裝： QFP-100
文件頁(yè)數(shù)： 39/98頁(yè)
文件大?。?/td> 584K
代理商： W6692ACF
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-44 -
1
Memory Base Address Reg.
IO Base Address Reg.
yes
1
0
Memory Base Address Reg.
Not Implemented
yes
0
1
IO Base Address Reg.
Not Implemented
no
0
Not Implemented
no
EEPROM empty
Memory Base Address Reg.
IO Base Address Reg.
PRE=0
In all cases, Memory Base Address register allocates 4096 byte spaces and IO Base Address register allocates 256 byte space.
Word 7 is Power Management Capability register. It replaces the chip's default value if EEPROM is not empty.
W6692A provides an EPCTL register for on-board access of the serial EEPROM. Software is responsible for creation of the
serial EEPROM’s waveform and timing and can read, write or erase the EEPROM's content.
7.9.2 8-bit Microprocessor Interface
At power up, the reset pin RST# must be asserted to initialize the chip. At rising edge of RST#, data value at CLK pin
determines the operation modes: active clock for PCI mode, HIGH for Intel bus mode, LOW for Motorola bus mode.
7.10 Peripheral Control
In PCI card with POTS application, the peripheral devices such as CODEC, DTMF and SLIC can be directly controlled by
W6692A, therefore eliminates the need for another PCI controller chip. The peripheral control function includes timer, interrupt
inputs and programmable IOs or microprocessor interface.
There are two timers implemented in W6692A: TIMR1 and TIMR2. TIMR1 is a long period timer whcich can be used to
control the cadence of ring tone. TIMR2 is a short period timer which can be used to generate the 20 Hz ring signal.
Address
Interrupt status
Interrupt mask
Output pin
Period
Cyclic
TIMR1
10H
DEXIR:T1EXP
DEXIM:T1EXP
No
(0..127)x 100 ms
yes (CNT=7)
TIMR2
4CH
DEXIR:TIN2
DEXIM:TIN2
TOUT2
(1..63) ms
yes(TMD=1)
There are two interrupt input pins : XINTIN0, XINTIN1. Whenever signal level changes (eith rising or falling), a maskable
interrupt is generated which in turn will make an interrupt request on PCI bus if it is unmasked. The interrupt status bits are
ISTA:XINT0, ISTA:XINT1. The mask bits are IMASK:XINT0, IMASK:XINT1. In addition, the signal level can be read at bits
SQR:XIND0, SQR;XIND1. These pins can be used for monitor of SLIC hook state and/or DTMF data valid status.
The IO interface can be programmed as simple IO (PCTL:XMODE=0) or 8-bit microprocessor interface (PCTL:XMODE=1).
As simple IOs, the pin data are accessed via XADDR and XDATA registers. The register data is output on the pin if its output
enable bit is set, the read data reflects the current level of pin. In this mode, a maximum of 11 IO ports are supported.
If programmed as 8-bit microprocessor mode, an 8-bit multiplexed bus is used to control peripheral deveces. The address and
data are multiplexed on XAD7-0. XALE is used for address latch and XRDB, XWRB are used for read/write strobe. To access
peripheral device, first write the desired address in XADDR register and then read/write data at XDATA register. In this mode, a
maximum of 256 byte ports can be supported by adding some glue TTLs on board.
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