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參數資料
| 型號： | W6694CD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | USB Bus ISDN S/T-Controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM, PLASTIC, LQFP-48 |
| 文件頁數： | 13/42頁 |
| 文件大?。?/td> | 567K |
| 代理商： | W6694CD |
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Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-13-
Publication Release Date: May, 2001
Revision 1.03
7. FUNCTIONAL DESCRIPTIONS
7.1 Microcontroller
The embedded 8 bit microcontroller core is a standard 80C51 MCU, operate at 24 MHz clock frequency. Its main function is
to transparently transfer data between USB, and ISDN/GCI/PCM interface. Data in D/B1/B2 channel is transferred as it is,
without further HDLC framing processing. All interface accept D/B1/B2 channel data, except for PCM interface, which
accept only B channel data. The data from each interface is first stored at individual register in the SFR (Special Function
Register) of microcontroller. Then the firmware, which resides in internal Mask ROM, is executed to constantly move data
between registers for different interface. The B channel receiving registers can be programmed by way of USB interface to
dynamically assign the data path between interfaces.
7.1.1 Special function register (SFR)
The SFRs, as in standard 80C51 architecture, reside in the upper 128 bytes of internal RAM, from address 80H to FFH.
W6694A specifically assign registers among SFRs exclusively for use of internal data transfer between interfaces. SFRs are
accessed by internal firmware only, and cannot be directly accessed by Bulk-OUT commands of USB interface. However,
some of the Bulk-OUT commands are used by host software to control FIFOs, such as CMDR1 and CMDR2.
TAble 7.1 W6694A specified SFR
SFR Addr.
C0
C1
C2
C3
C4
C5
C6
C9
CA
CB
CC
CD
CE
The reset values of above registers are all 0.
Symbol
INTFS
L1DDR
L1DDW
CB1DR
CB1DW
CB2DR
CB2DW
USBDDR
USBDDW
USBB1DR
USBB1DW
USBB2DR
USBB2DW
Meaning
Interface Status
Layer 1 D Channel Data Read
Layer 1 D Channel Data Write
Common B 1 Channel Data Read
Common B 1 Channel Data Write
Common B 2 Channel Data Read
Common B 2 Channel Data Write
USB D Channel Data Read
USB D Channel Data Write
USB B 1 Channel Data Read
USB B 1 Channel Data Write
USB B 2 Channel Data Read
USB B 2 Channel Data Write
Access
R
R
W
R
W
R
W
R
W
R
W
R
W
Bit Addressable
Yes
No
No
No
No
No
No
No
No
No
No
No
No
7.1.1.1 Interface Status Register
Values after reset: 00h
7
6
L1DRR
L1DWR
INTFS
Read_clear
Address C0h
5
4
3
2
1
0
CB1RR
CB1WR
CB2RR
CB2WR
UDRR
UDWR
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