參數(shù)資料
型號(hào)： W741E200
英文描述： 4-Bit Microcontroller
中文描述： 4位微控制器
文件頁(yè)數(shù)： 9/84頁(yè)
文件大?。?/td> 344K
代理商： W741E200
Preliminary W741E20X
Publication Release Date: March 1998
- 9 -
Revision A1
Clock Generator
The W741E20X provides a crystal or RC oscillation circuit selected by option codes to generate the
system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic
resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate
frequency is needed. When a crystal oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or
low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the
RC oscillator is used, a resistor in the range of 20 K
to 1.6 M
must be connected to XIN and XOUT,
as shown in Figure 3. The system clock frequency range is from 32 KHz to 4 MHz. One machine cycle
consists of a four-phase system clock sequence and can run up to 1
μ
S with a 4 MHz system clock.
XIN
XOUT
XIN
XOUT
or
Crystal
Resistor
32 KHz or
400K to 4MHz
Figure 3. Oscillator Configuration
Divider 0
Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown
in Figure 4. When the system starts, the divider is incremented by each system clock (Fosc). When an
overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt enable flag
has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set
(HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider 0 can be reset by executing
CLR DIVR0 instruction. If the oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1
periodically at each 500 mS interval.
Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program
from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set to
1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is F
OSC
/1024.
The input clock of the WDT can be switched to F
OSC
/16384 (or F
OSC
/1024) by executing the SET
PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction
CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT
overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun
overflow period is 468.75 mS when the system clock (F
OSC
) is 32 KHz and WDT clock input is
F
OSC
/1024. When the corresponding option code bit of the WDT is set to 0, the WDT function is
disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.
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