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參數(shù)資料
| 型號： | W78E374 |
| 英文描述： | Monitor Controller |
| 中文描述： | 監(jiān)測控制器 |
| 文件頁數(shù)： | 12/35頁 |
| 文件大小： | 186K |
| 代理商： | W78E374 |
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Preliminary W78E365
- 12 -
P2EAH, P2EAL:
The Port Enable Address Registers for Port2 as an Input Buffer/Output-Latched Port.
The I/O port enable address is need to assign when Port2 is defined as input buffer like a 74244, or a
output-latched logic like a 74373. The P2EAH contains the high-order byte of address, the P2EAL
contains the low-order byte of address. The following example shows how to program the Port 2 as a
output-latched port at address 5678H.
MOV P2EAL,#78H
; High-order byte of address to enable Port2 latch function.
MOV P2EAH,#56H
; Low-order byte of address to enable Port2 latch function.
MOV P2ECON,#02H
; Configure the Port2 as an output-latched port.
MOV DPTR,#5678H
; Move data 5678H to DPTR.
MOV A, #55H
; The pins P2.7
P2.0 will output and latch the value 55H.
When Port2 is configured as 74244 or 74373 function, the instruction " MOV P2,#XX " will write the
data #XX to P2 register only but not output to port pins P2.7
P2.0.
MOVX @DPTR, A
Port 2 Expanded Control Register(P2ECON).
P2ECON (AEH)
BIT
7
NAME
P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
= 1 : P4.3 is active high when pin P4.3 is defined as read and/or write strobe
signal.
= 0 : P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
P42CSINV The similarity definition as P43SINV.
P41CSINV The similarity definition as P43SINV.
P40CSINV The similarity definition as P43SINV.
-
Reserve
-
Reserve
P2CN1,
P2CN0
01 : Pins P2.7
P2.0 is input buffer port which the port enable address
depends on the content of P2EAL and P2EAH
10 : Pins P2.7
P2.0 is output-latched port which the port enable address
depends on the content of P2EAL and P2EAH.
11 : Undefined.
FUNCTION
6
5
4
3
2
1, 0
00 : Pins P2.7
P2.0 is the standard 8051 Port 2.
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