Publication Release Date: April 22, 2008 - 18 - Revision A8 5.13.1 CHPCON (BFH) BIT NAME FUNCTION 7 SWRESET (F04KMODE) Wh" />
參數(shù)資料
型號(hào)： W78E858A40PL
廠商： Nuvoton Technology Corporation of America
文件頁數(shù)： 10/35頁
文件大小： 0K
描述： IC MCU 8-BIT 32K FLASH 44-PLCC
標(biāo)準(zhǔn)包裝： 30
系列： W78
核心處理器： 8052
芯體尺寸： 8-位
速度： 40MHz
連通性： EBI/EMI，串行端口
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-PLCC
包裝： 管件
W78E858
Publication Release Date: April 22, 2008
- 18 -
Revision A8
5.13.1 CHPCON (BFH)
BIT
NAME
FUNCTION
7
SWRESET
(F04KMODE)
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This action will re-boot the microcontroller and start to normal operation.
To read this bit can determine that the F04KBOOT mode is running.
6
-
Reserve.
5
ENEEPROM Enable on-chip 128 bytes EEPROM.
4
ENAUXRAM Enable on-chip 512 bytes auxiliary RAM.
3
2
-
1
FBOOTSL
The loader program location selection.
= 0: loader program in 32K memory bank.
= 1: loader program in 4K memory bank.
0
FPROGEN
In system programming enable flag.
= 1: enable. The CPU switches to the programming flash mode after
entering the idle mode and waken up from interrupt. The CPU will
execute the loader program while in on-chip programming mode.
= 0: disable. The on-chip FLASH EPROM read-only. In-system
programmability is inhibit.
5.14 MXPSR (A2H)
BIT
NAME
FUNCTION
7
BUSY
EEPROM BUSY signal.
1: EEPROM is writing.
6-2
-
Reserved.
1-0
ADDRPNT
Address pointer by MOVX instruction
0: read or write lower 256 byte Auxiliary RAM by pointer of R0 or R1 register
1: read or write Higher 256 byte Auxiliary RAM by pointer of R0 or R1
register
2: 128 byte EEPROM by pointer of R0 or R1 register
5.15 Interrupt System
External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous
to do execution of any particular section of code. To tie the asynchronous actives of these functions to
normal program execution, a multiple-source, two-priority-level, nested interrupt system is provided.
The W78E858 acknowledges interrupt requests from fourteen sources as below:
INT0 and INT1
Timer0 and Timer1
UART serial I/O
INT2 to INT9 (at Port1)
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